Hi Friends, I have the following requirement.Please send suitable resimes only.
Position : System Design Engineer Location : San Jose,CA Duration : 6 +Months Requirements: § Experience in test/simulation/verification/validation/emulation/prototyping environments § Excellent working knowledge of Verilog § Excellent working knowledge of C § Master user of ISE/EDK tools and Synplify, especially in the area of complex IP blocks and system-level timing closure § Experience with Xilinx FPGAs § Experience with firmware / device driver programming § MS/BS in EE/CE/CS. § Good communication skills and methodical working practices § Strong desire to integrate and persistence to debug and root cause difficult problems Thanks & Regards *Pratap B* * **RapidIT, Inc**.* 5480 McGinnis Village Pl Suite#104 Alpharetta, GA 30005 mailto:pra...@rapiditinc.com <pra...@rapiditinc.com> www.rapiditinc.com Note: We respect your Online Privacy. This is not an unsolicited mail. Under Bills.1618 Title III passed by the 105th U.S. Congress this mail cannot be considered Spam as long as we include Contact information and a method to be removed from our mailing list. If you are not interested in receiving our e-mails then please reply with a "REMOVE" in the subject line and mention all the e-mail addresses to be removed with any e-mail addresses, which might be diverting the e-mails to you. We apologize for the inconvenience. --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "Embedded_C++_VC++" group. To post to this group, send email to Embedded_C_VC@googlegroups.com To unsubscribe from this group, send email to embedded_c_vc+unsubscr...@googlegroups.com For more options, visit this group at http://groups.google.co.in/group/Embedded_C_VC?hl=en -~----------~----~----~----~------~----~------~--~---
