Slavko Kocjancic пишет: > Alexey Starikovskiy pravi: > >> Slavko Kocjancic пишет: >> >> >>> Hello... >>> >>> I'm near finished new EPP board to be used for software stepgen. It has >>> 24 input and 24 output lines see: http://tinyurl.com/ycsuxb9 >>> >>> I don't know where to post all schematic/pcb design and manual when >>> finished but want to be free for all people. As many benchtop (cheap) >>> machines near all time had problem that just one or two parport pins >>> missing. >>> >>> >>> >> You could probably put it on EMC wiki. >> >> >>> ... and need little help to setup new software driver. I'm looking into >>> original parport driver and seems that can't be hard to make new one to >>> support that EPP extension. Just I'm not familiar with C and sooner or >>> latter can screw up thing. Can someone help? >>> >>> >>> >> What is the problem at hand? >> >> Alex. >> >> > > Well as I say the board in not finished yet (need day or two to finish) > As a matter of fact, I already see a big stopper in your board usefulness. You put optical isolation between logic and parallel port, I see 2 drawbacks of it: 1. parallel ports are quite weak these days (3.3v/~5mA), so driving LED from it directly is not bullet proof. 2. on both sides you have logic levels _always_. 3. machine equipment on the other side of your logic has very different set of voltages, 12, 24 volts are common, and sometimes you could find 48, your board does not allow to connect this equipment without yet another layer of optical isolation. 4. now you have common ground between all your logic and all 48 inputs and outputs (and your schematics can be stretched to 160)... I doubt that you could keep such ground clear of the machine noise.
In general, your design seem to be very close to UBOB board here: http://www.candcnc.com/UBOB.htm The problem with the above seems to be it's price, for about same money its possible to get much more capable board from MESA -- 7i43. > I need the new driver program. As C is stranger for me I can only modify > some line but for now can't rewrite new one. (and to put in system that > MAKE can realy compile that) > > So for access instead > > loadrt hal_parport cfg="0x0378" > addf parport.0.read base-thread 1 > addf parport.0.write base-thread -1 > > I wish something like > loadrt hal_EPPport cfg="0x0378" i=3 o=3 > addf EPPport.0.read base-thread 1 > addf EPPport.0.write base-thread -1 > > So new driver has same parameter for base address of port and two > aditional parameters of how many bytes the input has and the output has. > (wish to leave place to extend/shorten plate) > > So you just need to copy hal_parport.c to hal_epport.c and add hal_eppport.c to appropriate Submakefile. When you extend interface to allow 8*i and 8*o inputs and outputs and translate that into your command sequences. > Init sequence > write 0x04 at base addres+2 (to be sure EPP is in right direction) > Write 0x00 at base address+3 repeat 2 times > Write 0x00 at base address+4 repeat this 10 times > read from BaseAdr+1 and check if bit0 is 1. If 1 then report EPP > hardware doesn't respond (not connected) > > After that the write sequence should be: > > Write 1'st byte to BaseAddr+3 Address port (reset's counter and write > 1'st register) > Write 2'nd byte to BaseAddr+4 data port (increment port and write next > register) > Write 3'rd byte to BaseAddr+4 data port (increment port and write next > register) > .... repeat writting up to O= bytes to BaseAddr+4 > > then read > Read 1'st byte from BaseAddr+3 (reset counter and read from 1'st latch) > Read 2'nd byte from BaseAddr+4 (inc counter and read from next latch) > Read 3'nd byte from BaseAddr+4 (inc counter and read from next latch) > .... repeat reading up to I= bytes from BaseAddr+4 > > > Something like this.... > > > > > > > > > > > > ------------------------------------------------------------------------------ > Download Intel® Parallel Studio Eval > Try the new software tools for yourself. Speed compiling, find bugs > proactively, and fine-tune applications for parallel performance. > See why Intel Parallel Studio got high marks during beta. > http://p.sf.net/sfu/intel-sw-dev > _______________________________________________ > Emc-developers mailing list > [email protected] > https://lists.sourceforge.net/lists/listinfo/emc-developers > ------------------------------------------------------------------------------ Download Intel® Parallel Studio Eval Try the new software tools for yourself. Speed compiling, find bugs proactively, and fine-tune applications for parallel performance. See why Intel Parallel Studio got high marks during beta. http://p.sf.net/sfu/intel-sw-dev _______________________________________________ Emc-developers mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-developers
