On Tue, 16 Nov 2010, Matt Shaver wrote:

> Date: Tue, 16 Nov 2010 08:15:02 -0500
> From: Matt Shaver <m...@mattshaver.com>
> To: EMC developers <emc-developers@lists.sourceforge.net>
> Cc: p...@mesanet.com
> Subject: Re: [Emc-developers] 8i20 Support Patch
> 
> On Mon, 15 Nov 2010 17:47:37 -0800 (PST)
> "Peter C. Wallace" <p...@mesanet.com> wrote:
>
>> OK bitfile and assosciated pin file:
>> www.mesanet.com/software/parallel/sssvst.zip
>>
>> Had to drop two encoder counters to fit
>>
>> 2 sserial channels:
>> chan 0: tx1,rx5
>> chan 1: tx3,rx11
>>
>> cable (standard cat5 cut in half):
>> ch 0   ch 1
>>
>> txb1   txb3     orange/white
>> txa1   txa3     orange
>>
>> rxb5   rxb11    green/white
>> rxa5   rxa11    green
>>
>> +5V             brown&brown/white
>> gnd             blue&blue/white
>
> Thanks! Right now we only have one encoder (spindle). If we ever make a
> full servo machine, we'll just go to a card with a bigger FPGA.
>
> So, hopefully, we'll be able to spin up this motor before Thanksgiving,
> but if not, right after.
>
> Thanks Again,
> Matt
>

Actually I dont think theres a problem with servos on the 5I20 (its that delux 
48 bit step generator thats big). For example, theres a 12 channel analog 
servo config for the 5I20. Also a 6 channel sserial interface and 6 muxed 
encoders will fit so a 6 axis digital servo interface is possible in a 5I20 
(or 4I65) as well. What wont fit in the Spartan2 FPGAs is the resolver 
interface (too much block RAM and routing for the 32 bit processor), or 
combinations with lots of step gens, or where block RAMs are the limit (you 
are limited to one "smart" interface on the 5I20 due to block RAM limitations)


Peter Wallace
Mesa Electronics

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