On 07/21/2015 08:51 PM, Chris Lesiak wrote: > Instead of using __sync_synchronize, would you consider requiring --std=c11 > so that stdatomic.h can be used? > > That can give you just as much ordering as you require.
I don't see any memory barrier functions in stdatomic.h. http://en.cppreference.com/w/c/atomic The problem isn't about non-atomic memory access, it's about limiting memory access reordering. Intel (i386 and amd64) has strong memory ordering, so stores done by one processor will be seen by other processors in program order. ARM has weak memory ordering, so the stores may be seen by other processors in a different order than they were programmed. A special memory barrier instruction prevents reordering, and is required for correct execution of some of our code on ARM. https://en.wikipedia.org/wiki/Memory_ordering https://en.wikipedia.org/wiki/Memory_barrier Or am I missing something about your suggestion? -- Sebastian Kuzminsky ------------------------------------------------------------------------------ Don't Limit Your Business. Reach for the Cloud. GigeNET's Cloud Solutions provide you with the tools and support that you need to offload your IT needs and focus on growing your business. Configured For All Businesses. Start Your Cloud Today. https://www.gigenetcloud.com/ _______________________________________________ Emc-developers mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-developers
