I'm not sure I'm the most appropriate person to answer, but here's my
opinion. Doug Smith at Auspex (also a member of this ieee group) is probably
the best qualified to talk about ESD and other noise phenomena:

Back in the mid '80's when we were demonstrating ESD simulators (air
discharge only), we saw a lot of cases where EUT's survived higer voltages
-- 8 to 10kV, but failed when tested at a few kV. With the scopes at the
time, we could see faster rise times at the lower voltages (about 2-5kV),
slower risetimes at intermediate voltages (5-10kV) and faster risetimes
again at the higher voltages (>10kV). We attributed these low voltage
failures to the faster risetimes with air discharges below about 5kV. I I
think this scenereo is still valid, and we see risetimes of a few hundred
pico seconds below about 3kV. Risetimes do get to be slower at higher
voltages. David Pommerenke at HP has done a lot of recent work to
characterize human ESD with modern scopes and high bandwidth
instrumentation.

With contact mode testing, I'm not sure the same argument applies. With a
simulator that has very clean risetimes, the risetime is held constant (IEC
is .7 to 1ns) with voltage. di/dt in fact increases with voltage, which
would be evidence for more failures at higher voltages, but this doesn't
seem to be the case in practice. Nevertheless, people keep coming up with
cases where lower voltages cause failures where higher voltages are okay.

Some possibilities for the problem with contact mode:
1. Some simulator have a considerable amount of ringing on the rising edge
of the current waveform -- ESD Association work under WG14 -- also papers
published at past ESD Symposiums by HP and others. This ringing could be
inconsistant with voltage and be a significant contributor to failures.

2. Breakdowns inside the EUT in air across very small gaps could produce
risetimes well under 400ps. 

3.  Other ideas ???? 

In any case, it is still felt by members of IEC TC77B WG9 (now in the
process of completely re-evaluating IEC 61000-4-2) that testing at lower
voltages is required to insure a product is, in fact, immune to ESD. This
requirement will likely continue into any future version of the IEC
standard.

The latest draft of ANSI/IEEE C63.16-XXXX includes statements recommending
testing begin at the lowest voltage and progress to higher voltages -- 1kV
intervals for contact mode and 2kV intervals for air discharge. 

It's clear these requirements will go forward -- there's just too much
evidence for the existance of the phenomena, even though the reasons aren't
always clearly understood for a specific EUT.

Mike Hopkins
mhopk...@keytek.com

> -----Original Message-----
> From: b...@anritsu.com [SMTP:b...@anritsu.com]
> Sent: Thursday, August 19, 1999 6:56 PM
> To:   Mike Hopkins
> Subject:      fwd: re: EN50082-1:1997 & EN55024
> 
> Mike,
> 
> You are the most appropriate person to answer the question that why DUT
> could 
> fail at lower ESD voltage sometimes. Can you post your answer directly to
> the 
> emc-pstc group?
> 
> Thank you.
> Barry Ma
> b...@anritsu.com
> ---------- Original Text ----------
> 
> From: "Leslie Bai" <leslie_...@yahoo.com>, on 8/19/99 3:00 PM:
> To: Bailin Ma@MMDILAB@ACUS
> 
> Barry,
> 
> I agree with you but just wondering why
> "DUT got larger current at lower ESD 
> voltage. ...".
> 
> BTW, I called Anritsu early this week 
> requesting for a demonstration of "Site Master"
> but just couldn't get any reply yet. 
> 
> Rgds,
> Leslie
> 
> --- b...@anritsu.com wrote:
> > 
> > Jim,
> > 
> > You have been doing right thing. Those who directly
> > go to the highest ESD 
> > voltage level may thought if DUT can pass the
> > highest level it will certainly 
> > pass lower level. As a matter of fact, DUT could
> > possibly fail at lower level 
> > and pass at higher level. Because DUT got larger
> > current at lower ESD 
> > voltage. ...
> > 
> > Barry Ma
> > b...@anritsu.com
> > ---------- Original Text ----------
> > 
> > From: "Jim Hulbert" <hulbe...@pb.com>, on 8/19/99
> > 11:34 AM:
> > 
> > 
> > 
> > 
> > Immunity test standards EN50082-1:1997 and EN 55024
> > call out the basic 
> > standards
> > EN61000-4-2 and EN61000-4-5  for ESD and Surge.
> > 
> > EN61000-4-2, Section 5 starts out "The preferential
> > range of test levels for 
> > the
> > ESD test is given in table 1.  Testing shall also be
> > satisfied at the lower
> > levels given in table 1."   EN61000-4-5, Section 5
> > contains similar wording.
> > This is how we perform our compliance tests.   We
> > start at the lowest test
> > voltage levels from the respective tables and step
> > up to the test levels called
> > out in EN50082-1/ EN55024 (or higher, depending on
> > our own in-house product
> > spec.)
> > 
> > However, I have noticed that some test labs go
> > straight to the levels called 
> > out
> > in EN 50082-1/EN55024 and skip testing at the lower
> > levels.  I believe this
> > approach is incorrect because it does not conform to
> > the requirements of the
> > basic standard and is simply not a complete test.  
> > As explained in 
> > EN61000-4-5,
> > the non-linear current-voltage characteristics of
> > the equipment under test
> > should be considered and the test voltage should
> > therefore be increased by 
> > steps
> > up to the test level specified in the product
> > standard or test plan.   The same
> > rationale applies to ESD testing where
> > current-voltage characteristics are also
> > non-linear.
> > 
> > How do others approach these tests?  Are we adding
> > unnecessary test time by
> > starting at lower test voltages and stepping our way
> > up or are the test labs
> > that go straight to the maximum test levels
> > overlooking an important aspect of
> > the testing?
> > 
> > Jim Hulbert
> > Senior Engineer-EMC
> > Pitney Bowes
> > 
> > 
> > 
> > ---------
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