Hi All, This is a question regarding systems which use CompactPCI bus architecture. On a cPCI backplane the PCI clock is routed to every slot on the backplane with up to 7 peripheral slots possible on a normal backplane. My question is this: With the cPCI specification calling out specific trace lengths for clock traces on both the backplane itself and on peripheral cards, have other people experienced any unique EMI problems in trying to meet the design constraints associated with this synchronous bus; especially where there are unpopulated slots on the backplane?
Thanks in advance, Bill Fleury ***************Artesyn Communication Products, LLC****************** ******************************************************************** Bill Fleury Email: bi...@artesyncp.com Compliance Engineer Phone: 608-831-5500 8310 Excelsior Drive Fax: 608-831-8844 Madison, WI 53717 ******************************************************************** "The difficult can be done immediately, the impossible takes a little longer" (Army Corp of Engineers) ******************* Visit us at www.artesyn.com/cp ****************** <<Bill Fleury (E-mail).vcf>>
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