Hello Ravinder,

Your question is a bit difficult to answer.  You appear to have reached some
conclusions on what is going wrong in the circuit, but do you have really
good information on the problem?  I had a similar problem in an instrument
that had been designed prior to the widespread introduction of ESD tests.
It had divided grounds between analog and digial, just as you are thinking
here.  Close examination revealed that the two grounds would bounce
differently, causing logic problems and occasional lockups due to IC
substrate voltages going to unexpected levels.  So, dividing grounds without
understand exactly what's going on can be counterproductive.

In this case, actually closing the grounds together under the critical ICs
ended the problem (the separation at that point was not at all critical).
Simply put, you need to either (1) get the ground to stop bouncing so much
or (2) get all the associated PC lines to bounce in the same way.   For
example, it seems that your ASIC ground is bouncing, but the PC lines are
not.  Do they come from another board, perhaps?

If your group is considering a board re-spin, you owe it to yourself to
invest a few days with a good fast storage scope to track this monster as it
moves through your system, seeking True Ground (whatever it thinks that is).
Only then will you begin to gain an appreciation for how it moves and the
nature of the malfunctions.  You may be able to provide alternate
high-frequency paths and solve the problem without a board re-spin (and be a
hero).  I can assure you, however, that the board re-spin has no guarantee
of success unless you dig in there with a good scope.

Paul O'Shaughnessy
Affymetrix, Inc.

-----Original Message-----
From: Ravinder Ajmani [mailto:ajm...@us.ibm.com]
Sent: Tuesday, February 27, 2001 1:11 PM
To: emc-p...@ieee.org
Subject: ESD protection



Hi,
My question concerns providing ESD protection to analog circuitry on a
card.  Currently, I have a common ground for the entire card (2S2P).  For
reasons, the card has to be tied to chassis.  ESD discharge (air or
contact) to the chassis causes ground level to move up, thus reducing noise
margin and causing circuit malfunctioning.  The ASIC chip in question has
both analog and digital circuits, with separate decoupling capacitors for
analog and digital power.

Connecting a small (120 pF) capacitor directly across the analog power and
ground pins seems to provide some improvement in the ESD immunity.  We are
considering a board redesign.  Will it help if the ground plane below the
ASIC is sectioned to provide a separate analog ground, connected to main
ground at one location only near the decoupling capacitors, perhaps through
a small inductor.  Will this introduce other problems.  Any other ideas
!!!!!

Regards, Ravinder
PCB Development and Design Department
IBM Corporation
Email: ajm...@us.ibm.com
***************************************************************************
Always do right.  This will gratify some people and astonish the rest.
.... Mark Twain



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