Hi! Michael:
Thank you for your suggestion. It seems that copper fill that you and
several other guys mentioned does not applied in my board. For external
layers, you can implement the copper ring or, as other people suggested,
using copper fill but grounded it. In my case, I have a high-layer count
(>20), big board (about 40x60 cm) and also thin dielectrics. The main
problem is that certain area on internal layers (e.g., under DC converter)
is void of copper and that cause lamination voids and warpage.
Any suggestions on this ?
Regards
Perry
Michael Mertinooke wrote:
> >The question is, where do we find a compromised solution that makes
> everyone
> >happy ?
>
> The thieving areas are normally very rough, very wide (3/4 inch) borders
> around
> the boards, and are completely trimmed off when the bare boards are
> separated
> from the plating frames.
>
> Mike
-------------------------------------------
This message is from the IEEE EMC Society Product Safety
Technical Committee emc-pstc discussion list.
To cancel your subscription, send mail to:
majord...@ieee.org
with the single line:
unsubscribe emc-pstc
For help, send mail to the list administrators:
Jim Bacher: jim_bac...@mail.monarch.com
Michael Garretson: pstc_ad...@garretson.org
For policy questions, send mail to:
Richard Nute: ri...@ieee.org
