Yes indeed. My preference is for thieving to be done with "dots" or
"islands" small with respect to the shortest wavelength of concern. This is
because thieving can be constructed so as to resonate and aggravate an EMI
problem.
Some years ago, at an employer far away (grin), we had obtained compliance
on a computer using a plug-in processor board. On testing the first
production items, we found they were some dB over -- at 350 Mhz! It took
some time, but I found the PWB manufacturer had added a ring of thieving
material around the board. This ring was resonating at 350 Mhz and
significantly increasing the shielding required.
Chopping it up into strips made the problem go away.
(Many devices use so-called "ESD traces" to protect board-mounted devices
from being affected by ESD during maintenance. Unless care is taken with
these, they can act the same way as thieving copper above.)
Cortland
(cortland.richm...@usa.alcatel.com)
The post above does not represent my employer's opinions or policies
====================== (some snipped) ====================
List-Post: emc-pstc@listserv.ieee.org
Date: Tue, 16 Jan 2001 17:10:43 -0500
From: "Perry Qu" <perry...@alcatel.com>
Organization: Alcatel CID
Subject: [Fwd: [SI-LIST] : Copper balance]
Reply-To: "Perry Qu" <perry...@alcatel.com>
Hi!
We are looking for some advice on copper thieving on the PCB. The
concern is the EMC impact of the floating copper. Anyone is willing to
share his/her experience on the best configuration for high percentage
of copper coverage and low EMI at the same time ? Refer to the post to
SI list by my colleague Dorin on this issue.
Any advice on this will be greatly appreciated.
Regards
Perry Qu
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