In a former job, I prevailed on them to follow (mostly) a rule of 100 mils clearance between any inner OR outer layer conductor, and conducting objects directly exposed to ESD. This, after a helpful layout designer decided to improve things by adding internal ESD traces interlaced with power and ground. (Don't do that.)
However, the problems I've seen with clearance to surge and power-cross were associated with clearance to *vias* (and inside relays - a different matter) on the surface. The epoxy and FR4 material inside were more than sufficient to insulate against 2500 volt surge test voltages, even with 5 mil thickness. I believe the thread you recall was with respect to double insulation IN TRANSFORMERS. To prevent warping, keep the stackup symmetrical. Each layer should be matched by one the same thickness, on the other side. You will also need to insure copper is pretty evenly distributed. Cortland ------------------------------------------- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on "browse" and then "emc-pstc mailing list"
