I read in !emc-pstc that Plymale, Doug <do...@aiinet.com> wrote (in <ad59566a9d83864f871ae2e52503064005b...@aimail.aiinet.priv>) about 'PCB line spacing for NEBS 1089 1st Level lightning test.' on Mon, 11 Aug 2003: > Hello, > > How can I determine the best line spacing for high voltage pulses > on differential pairs? > Should the voltage be calculated at protection device's clamping > voltage? > How does the formula change for interlayer vs. top/bottom layer? > Is there any good reference material? > > IEC 60664 (multi-part). -- Regards, John Woodgate, OOO - Own Opinions Only. http://www.jmwa.demon.co.uk Interested in professional sound reinforcement and distribution? Then go to http://www.isce.org.uk PLEASE do NOT copy news posts to me by E-MAIL!
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