>> Jon tells me his amplifiers are optimized for 50 kHz PWM frequency. Does >> anyone know in what range the PWM frequency is adjustable on the Mesa >> M5i20 ? >> > > Its limited to ~33 KHz at the moment (33.3 MHz PCI clock /1024) > > It would be pretty easy to use the 50 MHz clock instead to the max would be > close to 50 KHz, or double that for 100 KHz or so maximum. > > 50 KHz is pretty high for PWM, as the switching losses in the HBridge go up, > and the dead time becomes more of the total cycle time. If the PWM is not > used directly to drive a HBridge, (just filtered to generate an analog > current threshold or something) then using the interleaved PWM option will > result lower ripple, so such a high PWM rate is not needed, but dont use the > interleaved option if the PWM drives an HBridge directly... > >> The manual talks about 10-bit PWM with a 33MHz clock so 1024 ticks >> equals 31us or 32.2 kHz >> is it possible to use a higher PWM frequency than this ? >> >> AW
OK I've made 4 new FPGA configurations: 1. HM5-4E - 4 axis 33 MHz PWM clock Same as before, just added R/O ID/REV/AXIS register and MCLK freq register ID/REV reads AA010004 (low half is # of axis), MCLK reads 33.3333 MHz 2. HM5-8E - 8 axis 33 MHz PWM clock Same as before, just added R/O ID/REV/AXIS register and MCLK freq register ID/REV reads AA010008 (low half is # of axis), MCLK reads 33.3333 MHz 3. HM5-4EH - 4 axis 100 MHz PWM clock Modified so basic clock for PWM and interrupt rate is 100 MHz ID/REV reads AA020004 (low half is # of axis), MCLK reads 100 MHz 4. HM5-8EH - 8 axis 100 MHz PWM clock Modified so basic clock for PWM and interrupt rate is 100 MHz ID/REV reads AA020008 (low half is # of axis), MCLK reads 100 MHz FPGA configurations 3 and 4 allow PWM rates up to 97.6 KHz (100 MHz/1024) Anders had asked for 66MHz master clock which I can do easily, (by doubling the PCI clock) but I figured that using the on card 50 MHz oscillator (which is used to generate the 100 MHz) has the advantage of known frequency, where the PCI bus clock could be anywhere from 32 to 33.3333 MHz. Also, having PWM rates up to 97.6 KHz allows some headroom if someone wants to play with optimum PWM rate for a given HBridge. If 66 MHz PWM clock is really desired, I could probably use two DCMs and quadruple the 50 MHz to 200 MHz then divide that by 3 for a known 66.66666 MHz, but cascading DCMs is a nuisance in Spartan2. I can send the source and bit files tommorow. (where?) Peter Wallace ------------------------------------------------------------------------- Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT & business topics through brief surveys - and earn cash http://www.techsay.com/default.php?page=join.php&p=sourceforge&CID=DEVDEV _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
