Andy Pugh wrote: > There are several supported by EMC2. > http://wiki.linuxcnc.org/emcinfo.pl?EMC2_Supported_Hardware > The feeling I get is that most people are using Pico or Mesa cards. > (My machine uses the Mesa 7i43 ($79) though my motivation was more IO > lines rather than better stepper speed. )
I must be missing something. There must be a term for this kind of hardware as opposed to I/O hardware like the PP(parallel-port) - (based on a FPGA or a dedicated fast uP with PWM I/O written in machine code) that takes 4 axis input of steps AND timing information instead of the OS timing each pulse the timing is in the cards hardware. I under stand what Jon is saying - the OS latency isn't good enough to keep the pulses coming perfectly smoothly at very high speed - you would get 'jitter'. So if you set up EMC to toggle a PP line at say 8hz - then looked at the square-wave on a fast scope - you will see jitter - and average jitter isn't the issue - it is max jitter. (There is no way to measure this in software.) This is what I'm getting at. Is a possible solution throwing hardware at it until it doesn't matter? Say: * Fast multi-core computer? * PCI-E I/O The problem is most of this hardware is set up to 'stream' really fast for moving digital video etc - but not timed random access - it relies on hardware FIFO buffers to cover the interrupts and the timing is generated on the graphics card. I'm thinking one could set up a buffer with the move pulses and timing and stream it with this hardware rather than depending on the OS for the timing. I write in machine code for embedded micros - I understand very well what is going on hardware wise. The problem I see is that there are always going to be interrupts that keep a PC from being real time (there are even hardware only interrupts that the OS can't do anything about). If the computer is super fast - or multi cored - the time to handle the interrupts can become so fast that the jitter is no longer an issue. I know enough about the 'real-time' kernel to know you can suspend most of the interrupts. But there is no way it can provide a 'perfect' output sq wave to the printer port. There will always be some jitter - ( a poorly written BIOS can make a problem here.) The jitter may be so little as to not matter, or it may matter. With PCI-E one should be able to write a DMA transfer to a PCI-E card that is independent of other things going on (this is what the E in PCI-E is all about). One could form a buffer in memory that is streamed to the card - the card would have a $5 FPGA chip with a PCI-E block. You could set up a Fifo buffer, and then the data would get clocked out 'perfectly'(there will always be 'some' aliasing jitter if the output is not a perfect multiple of the top clock). This would keep most of the work of ramping coordinating on the PC and in EMC as compared to a 'smart controller'. So what I'm asking is: " what is the proper term used with EMC for buffered and clocked pulse I/O cards? "step timing generator"? I'm also wondering does EMC compile a pulse list and timing before the move so there would be no computation latency, or is it generated on the fly? Going even further - most "stepper motors" aren't really steppers - they take step inputs and drive a DC servo-motor looking at position feed back. Somehow the history of the evolution of CNC has all this working in a disjointed way. We shouldn't be generating steps - we should have an I/O card/box that is really a coordinated multi-axis DC motor servo controller that EMC knows how to talk to. (Think about it this way - why tell someone to take one step towards the north. followed by many others when you really want his to just go to so far north at a particular speed? Further you have the same guy that is going east at the same - if one direction is falling behind a bit you can tell the other to slow as well to minimize path error - thus make a smoother path than a step interface can do. Jon Elson Wrote : > Mine is at > http://pico-systems.com/oscrc4/catalog/product_info.php?cPath=2&products_id=21 Hmm.. They call it a "Universal Stepper Controller" looks like 100ns - 4 axis - They claim 300ksteps/sec - What is the number on the big chip - looks like a xilinx - I'm guessing an FPGA. Same one that Evan Foss using? How does EMC talk to these? Does it just send it a Rate and a count for each axis and then a start command? Can it buffer two moves? Ramp? (The hardware probably has just linear ramps I would bet and no buffer - The USB receiver probably has a FIFO in it that could act as a buffer - Pulling in that buffer would cause some amount of pause as the next move is set up unless they have a dual data path where one is set up as the other one is running. -------------------------------------------------------------------------------- Karl Schmidt EMail [email protected] Transtronics, Inc. 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