On Fri, 13 Jul 2012, Hugh Wylie wrote: > > > Something I wish to know (which our Mesa colleagues will I am sure answer) > is the tradeoff between control loop time and number of pulse generator and > stepper motor instances invoked in the 5i23. How is the stepper control loop > cycle time affected by pwm/pdm frequencies (I guess only FPGA processor > resource sharing between 5i23 tasks)? Has maximum step rate been graphed > against number of instances? Is similar data available for other family > members? Appears to me that to optimise 5i23 performance for stepper > control, one should keep pwmgen frequency around 20kHz (accepting pwmgen > task is trivial vs stepper control). Racking becomes worse as we increase > jog speed to a step interval around 50us (and concurrent motion on all > joints). >
There is no connection between PWM/PDM frequency and the stepgenerators. all hardware runs in parallel, only CPU side hardware access is serialized (for reading input registers and writing output registers) The 5I23 is capable of running more than 24 Step generators at a 12 MHz output rate (we have customers running 48 stepgens simultaneously on a 5I22 in a non LinuxCNC real time linux environment) PWM/PDM is likewise all done in parallel in the hardware so the number of PWM channels or frequency has no effect on other hardware in the FPGA. Is it possible you have a software PWM/PDM setup? (you should not! nor should you have a base thread) Peter Wallace Mesa Electronics ------------------------------------------------------------------------------ Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ _______________________________________________ Emc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-users
