On 12/31/2016 09:18 PM, Gene Heskett wrote: [snip] >> However, if the reference ground is not equal at both ends of the >> signal line, then you are in trouble. This is why you would use a >> balanced line (differential), which is not absolutely referenced to >> ground, but switches on the differential (and you can clamp the >> lines). >> > Do you know of a 4 wire to 8 wire and back interface that can function at > 32 megabaud and doesn't cost 5 grand+? Neither do I. :) Laser diodes > and detectors that could handle 2x the video speed needed to hit an HDTV > transmitter would be required, times 4 to do it optically. > > There are capacitatively coupled chips I have seen the announcements for, > intended to steal some of the jobs the MOC chips are doing, but no clue > as to their useable bandwidth. I'll see what google says. > > A paper by Silabs > <https://www.silabs.com/Support%20Documents/TechnicalDocs/CMOS-Digital-Isolators-WP.pdf> > says the are using a nominally 10 megahertz carrier in a cmos circuit, > about 30x too slow for this. > > Searching further, TI has a family of them, 3 channels one way, 1 the > other, would only need one, at 3.49 in 1k lots, claims 100 megahertz > bandwidth. I'll see how much power it needs, and what the small qty > price might be. Not available, so I've ordered samples of 2 variations, > one of which is inverting but I don't see which is which. Its an SOIC > package, dunno if I could hack a pcb for that. > > Perhaps this might be the better method?
Actually, I do know how to do it cheaper than $5k. The Silicon Labs isolator chips are rated up to 150 Mb/s, so that is not a real issue. A LVDS driver and receiver can be had for $1..2. Then you need some support logic and power management (power isolation). All in all, a three channel system on CAT3 (CAT5 patch-) cabling would be in the order of $20..30 in components. Add some overhead and we are at about $50 (disregarding my hours of designing the circuit). (isolator, see f.ex. http://www.mouser.com/ds/2/368/Si864x-51666.pdf) A proper digital balanced isolator is no rocket science and does not need to be too expensive. It just takes time to design, build and test. However, the real issue is the distance you can carry the signal due to propagation delay. If you use bidirectional SPI, then you have clock, data-out (MOSI) and data-in (MISO). At 32MHz clock you have a maximum of 15.6 ns of round-trip delay that can be tolerated on the data-in with respect to the clock (half-period). That translates into 1.5 meters(*) of cable (velocity at ~0.6c) and we ignore all the intermediate electronics' propagation delays. Adding in a buffer/driver (whatever type) at the cable ends introduces roughly 5..6 ns delay if you are lucky. That would reduce the effective length to under one meter. Not all is lost; If you send much more data than you receive, then you can still send at high speed where all signals are propagation balanced. Then, for reading, you reduce the SPI clock frequency considarably to take the round-trip propagation delay into account. (*) the signal-delay is measured round-trip which is twice the cable's length. The SPI master sends a clock, traverses the cable, causes a MISO change, traverses the cable, read by master. -- Greetings Bertho (disclaimers are disclaimed) ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, SlashDot.org! http://sdm.link/slashdot _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
