Hi, I am trying to use the yaskawa sigma 7 servopack with the igh master. I am unable to get it into op state. It always gets stuck at pre-op state. Also there are many datagram timeouts. I have attached logs as well as my xenomai application which I am using for this. It would be really helpful if somebody could guide me in the right direction.
Regards, Rahul
Linux version 2.6.33 (root@linux-0mmn) (gcc version 4.3.6 (Buildroot 2011.11) ) #1 Tue Apr 11 09:38:47 CDT 2017 CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177 CPU: VIVT data cache, VIVT instruction cache Machine: Atmel AT91SAM9G20-EK Memory policy: ECC disabled, Data cache writeback Clocks: CPU 396 MHz, master 132 MHz, main 18.432 MHz Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16256 Kernel command line: console=ttyS1,115200 root=/dev/mtdblock1 mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) rw rootfstype=jffs2 PID hash table entries: 256 (order: -2, 1024 bytes) Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) Memory: 64MB = 64MB total Memory: 61120KB available (3196K code, 333K data, 128K init, 0K highmem) Hierarchical RCU implementation. RCU-based detection of stalled CPUs is enabled. NR_IRQS:192 AT91: 96 gpio irqs in 3 banks AT91 I-pipe timer: div: 128, freq: 1.032000 MHz, wrap: 63.503875 ms I-pipe 1.16-01: pipeline enabled. Console: colour dummy device 80x30 Calibrating delay loop... 197.83 BogoMIPS (lpj=989184) Mount-cache hash table entries: 512 CPU: Testing write buffer coherency: ok devtmpfs: initialized NET: Registered protocol family 16 AT91: Power Management AT91: Starting after user reset bio: create slab <bio-0> at 0 SCSI subsystem initialized usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb Advanced Linux Sound Architecture Driver Version 1.0.21. Switching to clocksource at91_tc0 NET: Registered protocol family 2 IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 2048 (order: 2, 16384 bytes) TCP bind hash table entries: 2048 (order: 1, 8192 bytes) TCP: Hash tables configured (established 2048 bind 2048) TCP reno registered UDP hash table entries: 256 (order: 0, 4096 bytes) UDP-Lite hash table entries: 256 (order: 0, 4096 bytes) NET: Registered protocol family 1 RPC: Registered udp transport module. RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. NetWinder Floating Point Emulator V0.97 (double precision) I-pipe: Domain Xenomai registered. Xenomai: hal/arm started. Xenomai: scheduling class idle registered. Xenomai: scheduling class rt registered. Xenomai: real-time nucleus v2.5.6 (Wormhole Wizards) loaded. Xenomai: starting native API services. Xenomai: starting POSIX services. Xenomai: starting RTDM services. JFFS2 version 2.2. (NAND) (SUMMARY) Ā© 2001-2006 Red Hat, Inc. msgmni has been set to 119 io scheduler noop registered (default) atmel_usart.0: ttyS0 at MMIO 0xfefff200 (irq = 1) is a ATMEL_SERIAL atmel_usart.1: ttyS1 at MMIO 0xfffb0000 (irq = 6) is a ATMEL_SERIAL console [ttyS1] enabled atmel_usart.2: ttyS2 at MMIO 0xfffb4000 (irq = 7) is a ATMEL_SERIAL brd: module loaded loop: module loaded ssc ssc.0: Atmel SSC device at 0xc48c0000 (irq 14) NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron NAND 256MiB 3,3V 8-bit) AT91 NAND: 8-bit, Software ECC Scanning device for bad blocks Creating 3 MTD partitions on "atmel_nand": 0x000000000000-0x000000400000 : "Bootstrap" 0x000000400000-0x000004000000 : "Partition 1" 0x000004000000-0x000010000000 : "Partition 2" atmel_spi atmel_spi.0: Atmel SPI Controller at 0xfffc8000 (irq 12) usbmon: debugfs is not available ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver at91_ohci at91_ohci: AT91 OHCI at91_ohci at91_ohci: new USB bus registered, assigned bus number 1 at91_ohci at91_ohci: irq 20, io mem 0x00500000 hub 1-0:1.0: USB hub found hub 1-0:1.0: 2 ports detected Initializing USB Mass Storage driver... usbcore: registered new interface driver usb-storage USB Mass Storage support registered. udc: at91_udc version 3 May 2006 mice: PS/2 mouse device common for all mice input: gpio-keys as /devices/platform/gpio-keys/input/input0 rtc-at91sam9 at91_rtt.0: rtc core: registered at91_rtt as rtc0 IRQ 1/rtc0: IRQF_DISABLED is not guaranteed on shared IRQs rtc-at91sam9 at91_rtt.0: rtc0: SET TIME! Registered led device: ds5 Registered led device: ds1 usbcore: registered new interface driver usbhid usbhid: USB HID core driver ALSA device list: No soundcards found. TCP cubic registered NET: Registered protocol family 17 rtc-at91sam9 at91_rtt.0: hctosys: unable to read the hardware clock Empty flash at 0x001fe914 ends at 0x001ff000 VFS: Mounted root (jffs2 filesystem) on device 31:1. devtmpfs: mounted Freeing init memory: 128K ec_rt_dpr: module license 'unspecified' taints kernel. Disabling lock debugging due to kernel taint EtherCAT: Master driver 1.5.2 2eff7c993a63 EtherCAT 0: Registering RTDM device EtherCAT. EtherCAT: 1 master waiting for devices. (null): invalid hw address, using random EtherCAT: Accepting C2:08:C4:78:DD:95 as main device for master 0. EtherCAT 0: Starting EtherCAT-IDLE thread. ecdev_open was successful EtherCAT 0: Link state of ecm0 changed to UP. EtherCAT WARNING 0: 1 datagram TIMED OUT! EtherCAT WARNING 0: 17 datagrams TIMED OUT! EtherCAT WARNING 0: 17 datagrams TIMED OUT! EtherCAT WARNING 0: 17 datagrams TIMED OUT! EtherCAT WARNING 0: 17 datagrams TIMED OUT! EtherCAT WARNING 0: 17 datagrams TIMED OUT! Welcome to Buildroot buildroot login: EtherCAT WARNING 0: 17 datagrams TIMED OUT! EtherCAT WARNING 0: 17 datagrams TIMED OUT! EtherCAT WARNING 0: 17 datagrams TIMED OUT! EtherCAT WARNING 0: 17 datagrams TIMED OUT! EtherCAT WARNING 0: 17 datagrams TIMED OUT! EtherCAT WARNING 0: 17 datagrams TIMED OUT! EtherCAT WARNING 0: 17 datagrams TIMED OUT! EtherCAT WARNING 0: 17 datagrams TIMED OUT! EtherCAT WARNING 0: 17 datagrams TIMED OUT! EtherCAT WARNING 0: 17 datagrams TIMED OUT! EtherCAT WARNING 0: 17 datagrams TIMED OUT! EtherCAT WARNING 0: 17 datagrams TIMED OUT! EtherCAT WARNING 0: 17 datagrams TIMED OUT!
/*: main.c,v 3bdd7a747fae 2012/09/20 13:28:25 fp $ * * Copyright (C) 2009-2010 Moehwald GmbH B. Benner * 2011 IgH Andreas Stewering-Bone * 2012 Florian Pose <f...@igh-essen.com> * * This file is part of the IgH EtherCAT master * * The IgH EtherCAT Master is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License version 2, as * published by the Free Software Foundation. * * The IgH EtherCAT master is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General * Public License for more details. * * You should have received a copy of the GNU General Public License along * with the IgH EtherCAT master. If not, see <http://www.gnu.org/licenses/>. * * --- * * The license mentioned above concerns the source code only. Using the * EtherCAT technology and brand is only permitted in compliance with the * industrial property and similar rights of Beckhoff Automation GmbH. * *****************************************************************************/ #include <errno.h> #include <signal.h> #include <stdio.h> #include <string.h> #include <sys/resource.h> #include <sys/time.h> #include <sys/types.h> #include <unistd.h> #include <sys/mman.h> #include <rtdm/rtdm.h> #include <native/task.h> #include <native/sem.h> #include <native/mutex.h> #include <native/timer.h> #include <rtdk.h> #include <pthread.h> #include "ecrt.h" #include <time.h> RT_TASK my_task; static int run = 1; /****************************************************************************/ // EtherCAT static ec_master_t *master = NULL; static ec_master_state_t master_state = {}; static ec_domain_t *domain1 = NULL; static ec_domain_state_t domain1_state = {}; static uint8_t *domain1_pd = NULL; static ec_domain_t *domain2 = NULL; static ec_domain_state_t domain2_state = {}; static uint8_t *domain2_pd = NULL; //static ec_slave_config_t *sc_dig_out_01 = NULL; /****************************************************************************/ // process data #define Drive01_Pos 0, 0 //#define BusCoupler01_Pos 0, 0 #define DigOutSlave01_Pos 0, 1 #define Yaskawa_Sigma7 0x00000539, 0x02200301 // offsets for PDO entries static unsigned int off_dig_out0 = 0; static unsigned int off_dig_out1 = 0; static unsigned int off_dig_in0 = 0; static unsigned int off_dig_in1 = 0; const static ec_pdo_entry_reg_t domain1_regs[] = { {Drive01_Pos, Yaskawa_Sigma7, 0x6041, 0, &off_dig_in0, NULL}, {Drive01_Pos, Yaskawa_Sigma7, 0x6040, 0, &off_dig_out0, NULL}, {} }; const static ec_pdo_entry_reg_t domain2_regs[] = { {Drive01_Pos, Yaskawa_Sigma7, 0x6064, 0, &off_dig_in1, NULL}, {Drive01_Pos, Yaskawa_Sigma7, 0x607a, 0, &off_dig_out1, NULL}, {} }; /****************************************************************************/ /* Slave 0, "Yaskawa Sigma 7" * Vendor ID: 0x00000539 (1337 decimal) * Product code: 0x02200301 * Revision number: */ //initialize pdos static ec_pdo_entry_info_t yaskawa_sigma7_pdoEntries[] = { {0x6040, 0x00, 16}, // pg 8-21 control (rw) {0x607a, 0x00, 32}, // pg 8-30 target position (rw) (for cyclic sync pos mode) {0x60b1, 0x00, 32}, // pg 8-37 velocity offset (rw) (for cyclic sync pos mode) {0x6072, 0x00, 16}, // pg 8-40 max torque (rw) in 0.1% increments, what is +ve torque lim and - torque lim? pdo or sdo?? {0x60fe, 0x01, 32}, // pg 8-44 outputs (rw) (bits 17, 18, 19 control outputs 1, 2, 3) {0x60b8, 0x00, 16}, // pg 8-41 latchControl (rw) (bits: 0 enable latch, 1 single/continuous trigger, // 2 0=latch on S14 | 1=latch on C, 4 enable latch sampling???) {0x6060, 0x00, 8}, // pg 8-28 mode of operation (rw) (8=cyclic pos, 9=cyclic vel) {0x6041, 0x00, 16}, // pg 8-23 status (r) {0x6064, 0x00, 32}, // pg 8-34 actual position (r) {0x606c, 0x00, 32}, // pg 8-38 actual velocity (r) required?? {0x6077, 0x00, 16}, // pg 8-39 actual torque (r) {0x60f4, 0x00, 32}, // pg 8-35 actual following error (r) {0x60fd, 0x00, 32}, // pg 8-43 inputs (r) (available inputs: 0 (rev lim), 1 (fwd lim), 2 (hm), // 16 - 22 (via CN1), 25 - 25 (via base block)) {0x60ba, 0x00, 32}, // pg 8-42 latchPos (r) (via touch probe 1) {0x60b9, 0x00, 16}, // pg 8-42 latchStatus (r) (bits: 0 latch enabled, 1 latched, 7 latched toggle (for continuous mode)) {0x6061, 0x00, 8}, // pg 8-28 current mode of operation {0x6098, 0x00, 8}, // pg 8-32 homing mode (rw) note: rw but we only want to read current value (setting new value by sdo) {0x603f, 0x00, 16}, // pg 8-21 last error code {0x6062, 0x00, 32}, // pg 8-34 position demand value (r) }; static ec_pdo_info_t yaskawa_sigma7_pdos[] = { {0x1600, 7, yaskawa_sigma7_pdoEntries + 0}, {0x1a00, 8, yaskawa_sigma7_pdoEntries + 7}, {0x1a01, 4, yaskawa_sigma7_pdoEntries + 15}, }; static ec_sync_info_t yaskawa_sigma7_syncs[] = { //################## {0, EC_DIR_OUTPUT, 0, NULL, EC_WD_DISABLE}, {1, EC_DIR_INPUT, 0, NULL, EC_WD_DISABLE}, {2, EC_DIR_OUTPUT, 1, yaskawa_sigma7_pdos + 0, EC_WD_ENABLE}, {3, EC_DIR_INPUT, 2, yaskawa_sigma7_pdos + 1, EC_WD_DISABLE}, {0xff} }; static unsigned int sync_ref_counter = 0; //Not used anywhere /* #define FREQUENCY 1000 #define NSEC_PER_SEC (1000000000L) #define PERIOD_NS (NSEC_PER_SEC / FREQUENCY) #define TIMESPEC2NS(T) ((uint64_t) (T).tv_sec * NSEC_PER_SEC + (T).tv_nsec) #define EL70X1_STEPSPERREV 200 */ /***************************************************************************** * Realtime task ****************************************************************************/ void rt_check_domain_state(void) { ec_domain_state_t ds1 = {}; ec_domain_state_t ds2 = {}; //domain 1 ecrt_domain_state(domain1, &ds1); if (ds1.working_counter != domain1_state.working_counter) { rt_printf("Domain1: WC %u.\n", ds1.working_counter); } if (ds1.wc_state != domain1_state.wc_state) { rt_printf("Domain1: State %u.\n", ds1.wc_state); } domain1_state = ds1; //domain 2 ecrt_domain_state(domain2, &ds2); if (ds2.working_counter != domain2_state.working_counter) { rt_printf("Domain2: WC %u.\n", ds2.working_counter); } if (ds2.wc_state != domain2_state.wc_state) { rt_printf("Domain2: State %u.\n", ds2.wc_state); } domain2_state = ds2; } /****************************************************************************/ void rt_check_master_state(void) { ec_master_state_t ms; ecrt_master_state(master, &ms); if (ms.slaves_responding != master_state.slaves_responding) { rt_printf("%u slave(s).\n", ms.slaves_responding); } if (ms.al_states != master_state.al_states) { rt_printf("AL states: 0x%02X.\n", ms.al_states); } if (ms.link_up != master_state.link_up) { rt_printf("Link is %s.\n", ms.link_up ? "up" : "down"); } master_state = ms; } /****************************************************************************/ void my_task_proc(void *arg) { int cycle_counter = 0; unsigned int blink = 0; unsigned int pos = 0; unsigned int status = 0; struct timespec time; rt_task_set_periodic(NULL, TM_NOW, 10000000); // ns while (run) { rt_task_wait_period(NULL); cycle_counter++; // receive EtherCAT frames ecrt_master_receive(master); ecrt_domain_process(domain1); ecrt_domain_process(domain2); rt_check_domain_state(); if (!(cycle_counter % 1000)) { rt_check_master_state(); } if(!(cycle_counter % 200)){ blink = !blink; } //EC_WRITE_U8(domain1_pd + ) EC_WRITE_U8(domain1_pd + off_dig_out0, blink ? 0x0 : 0x0F); // send process data ecrt_domain_queue(domain1); ecrt_domain_queue(domain2); ecrt_master_send(master); } } /**************************************************************************** * Signal handler ***************************************************************************/ void signal_handler(int sig) { run = 0; } /**************************************************************************** * Main function ***************************************************************************/ int main(int argc, char *argv[]) { ec_slave_config_t *sc_dig_out_01; int ret; /* Perform auto-init of rt_print buffers if the task doesn't do so */ rt_print_auto_init(1); // signal(SIGTERM, signal_handler); // signal(SIGINT, signal_handler); mlockall(MCL_CURRENT | MCL_FUTURE); printf("Requesting master...\n"); master = ecrt_request_master(0); if (!master) { return -1; } printf("Create domain1\n"); domain1 = ecrt_master_create_domain(master); if (!domain1) { return -1; } printf("Create domain2\n"); domain2 = ecrt_master_create_domain(master); if (!domain2) { return -1; } //getting slave configuration printf("Trying to get slave config"); sc_dig_out_01 = ecrt_master_slave_config(master, DigOutSlave01_Pos, Yaskawa_Sigma7); if (!sc_dig_out_01) { fprintf(stderr, "Failed to get slave configuration.\n"); return -1; } //configure PDOs printf("Configure the PDOs\n"); if (ecrt_slave_config_pdos(sc_dig_out_01, EC_END, yaskawa_sigma7_syncs)) { fprintf(stderr, "Failed to configure PDOs.\n"); return -1; } // Create ecrt_slave_config_reg_pdo_entry - one call per pdo entry you want to interact if(ecrt_slave_config_reg_pdo_entry(sc_dig_out_01, Drive01_Pos, domain1, NULL)){ printf("Failed to register pdo entry\n"); return -1; } if(ecrt_slave_config_reg_pdo_entry(sc_dig_out_01, Drive01_Pos, domain2, NULL)){ printf("Failed to register pdo entry\n"); return -1; } // or the below method can be used. printf("ecrt_domain_reg_pdo_entry_list()\n"); if (ecrt_domain_reg_pdo_entry_list(domain1, domain1_regs)) { fprintf(stderr, "PDO entry registration failed!\n"); return -1; } if (ecrt_domain_reg_pdo_entry_list(domain2, domain2_regs)) { fprintf(stderr, "PDO entry registration failed!\n"); return -1; } // Since we are dealing with only one slave, we do not need dc. Hence commenting it out //ecrt_slave_config_dc(sc, 0x0, 10000000, 0, 0, 0); printf("Activating Master\n"); if (ecrt_master_activate(master)) { printf("Could not activate Master\n"); return -1; } printf("ecrt_domain_get_data()\n"); if (!(domain1_pd = ecrt_domain_data(domain1))) { fprintf(stderr, "Failed to get domain1 data pointer.\n"); return -1; } // domain 2 printf("ecrt_domain_get_data()\n"); if (!(domain2_pd = ecrt_domain_data(domain2))) { fprintf(stderr, "Failed to get domain1 data pointer.\n"); return -1; } ret = rt_task_create(&my_task, "my_task", 0, 80, T_FPU); if (ret != 0) { fprintf(stderr, "Failed to create task: %s\n", strerror(-ret)); return -1; } printf("Starting my_task...\n"); ret = rt_task_start(&my_task, &my_task_proc, NULL); if (ret != 0) { fprintf(stderr, "Failed to start task: %s\n", strerror(-ret)); return -1; } while (run) { sched_yield(); } printf("Deleting realtime task...\n"); rt_task_delete(&my_task); printf("End of Program\n"); ecrt_release_master(master); return 0; } /****************************************************************************/
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