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new 79adb692a2 rvv: add optimized h264 intra prediction functions
79adb692a2 is described below
commit 79adb692a2720647e9dbe57de33fd50b41db295c
Author: Tristan Matthews <[email protected]>
AuthorDate: Sun Jul 20 12:13:00 2025 +0000
Commit: Marvin Scholz <[email protected]>
CommitDate: Sun Jul 5 17:47:56 2026 +0000
rvv: add optimized h264 intra prediction functions
Reviewed-by: Nathan E. Egge <[email protected]>
Reviewed-by: Rémi Denis-Courmont <[email protected]>
Benched on SpaceMIT K1 for VLEN 256 and CanMV-K230 for VLEN 128.
C RVV256 C RVV128
pred8x8_horizontal_8 31.1 19.8 (1.57x) 39.9 19.3 (2.07x)
pred8x8_plane_8 175.6 78.0 (2.25x) 175.7 89.6 (1.96x)
pred16x16_dc_8 56.1 44.2 (1.27x) 73.6 53.2 (1.38x)
pred16x16_dc_128_8 21.1 18.5 (1.14x) 37.2 28.3 (1.31x)
pred16x16_horizontal_8 84.9 37.3 (2.28x) 106.8 47.4 (2.25x)
pred16x16_left_dc_8 43.6 37.9 (1.15x) 60.8 47.4 (1.28x)
pred16x16_plane_8 644.8 130.0 (4.96x) 610.8 182.3 (3.35x)
pred16x16_top_dc_8 36.7 29.2 (1.26x) 53.8 38.5 (1.40x)
pred16x16_vertical_8 27.9 19.2 (1.45x) 42.3 28.9 (1.46x)
---
libavcodec/h264pred.c | 2 +
libavcodec/h264pred.h | 3 +-
libavcodec/riscv/Makefile | 2 +
libavcodec/riscv/h264_intrapred_init.c | 113 ++++++
libavcodec/riscv/h264_intrapred_rvv.S | 679 +++++++++++++++++++++++++++++++++
5 files changed, 798 insertions(+), 1 deletion(-)
diff --git a/libavcodec/h264pred.c b/libavcodec/h264pred.c
index fbd8d2b91d..5de0d6f846 100644
--- a/libavcodec/h264pred.c
+++ b/libavcodec/h264pred.c
@@ -598,5 +598,7 @@ av_cold void ff_h264_pred_init(H264PredContext *h, int
codec_id,
ff_h264_pred_init_mips(h, codec_id, bit_depth, chroma_format_idc);
#elif ARCH_LOONGARCH
ff_h264_pred_init_loongarch(h, codec_id, bit_depth, chroma_format_idc);
+#elif ARCH_RISCV
+ ff_h264_pred_init_riscv(h, codec_id, bit_depth, chroma_format_idc);
#endif
}
diff --git a/libavcodec/h264pred.h b/libavcodec/h264pred.h
index cb008548fc..8ac5088b34 100644
--- a/libavcodec/h264pred.h
+++ b/libavcodec/h264pred.h
@@ -126,5 +126,6 @@ void ff_h264_pred_init_mips(H264PredContext *h, int
codec_id,
const int bit_depth, const int chroma_format_idc);
void ff_h264_pred_init_loongarch(H264PredContext *h, int codec_id,
const int bit_depth, const int
chroma_format_idc);
-
+void ff_h264_pred_init_riscv(H264PredContext *h, int codec_id,
+ const int bit_depth, const int chroma_format_idc);
#endif /* AVCODEC_H264PRED_H */
diff --git a/libavcodec/riscv/Makefile b/libavcodec/riscv/Makefile
index 28d745cfe3..ff063afc35 100644
--- a/libavcodec/riscv/Makefile
+++ b/libavcodec/riscv/Makefile
@@ -33,6 +33,8 @@ RVV-OBJS-$(CONFIG_H264CHROMA) += riscv/h264_mc_chroma.o
OBJS-$(CONFIG_H264DSP) += riscv/h264dsp_init.o
RVV-OBJS-$(CONFIG_H264DSP) += riscv/h264addpx_rvv.o riscv/h264dsp_rvv.o \
riscv/h264idct_rvv.o riscv/h264idct_dequant_rvv.o
+OBJS-$(CONFIG_H264PRED) += riscv/h264_intrapred_init.o
+RVV-OBJS-$(CONFIG_H264PRED) += riscv/h264_intrapred_rvv.o
OBJS-$(CONFIG_H264QPEL) += riscv/h264qpel_init.o
RVV-OBJS-$(CONFIG_H264QPEL) += riscv/h264qpel_rvv.o
OBJS-$(CONFIG_HEVC_DECODER) += riscv/hevcdsp_init.o
diff --git a/libavcodec/riscv/h264_intrapred_init.c
b/libavcodec/riscv/h264_intrapred_init.c
new file mode 100644
index 0000000000..4497645206
--- /dev/null
+++ b/libavcodec/riscv/h264_intrapred_init.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2025 Tristan Matthews <[email protected]>
+ *
+ * This file is part of FFmpeg.
+ *
+ * FFmpeg is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * FFmpeg is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with FFmpeg; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stddef.h>
+#include <stdint.h>
+#include "config.h"
+#include "libavutil/attributes.h"
+#include "libavutil/cpu.h"
+#include "libavutil/riscv/cpu.h"
+#include "libavcodec/codec_id.h"
+#include "libavcodec/h264pred.h"
+
+#define PRED8x8(TYPE, DEPTH, SUFFIX) \
+void ff_pred8x8_ ## TYPE ## _ ## DEPTH ## _ ## SUFFIX (uint8_t *src, \
+ ptrdiff_t stride);
+
+#define PRED16x16(TYPE, DEPTH, SUFFIX) \
+void ff_pred16x16_ ## TYPE ## _ ## DEPTH ## _ ## SUFFIX (uint8_t *src, \
+ ptrdiff_t stride);
+
+/* 8-bit versions */
+PRED8x8(horizontal, 8, rvv_vl128)
+PRED8x8(horizontal, 8, rvv_vl256)
+PRED8x8(plane, 8, rvv_vl128)
+PRED8x8(plane, 8, rvv_vl256)
+PRED16x16(horizontal, 8, rvv_vl128)
+PRED16x16(horizontal, 8, rvv_vl256)
+PRED16x16(vertical, 8, rvv_vl128)
+PRED16x16(vertical, 8, rvv_vl256)
+PRED16x16(dc, 8, rvv_vl128)
+PRED16x16(dc, 8, rvv_vl256)
+PRED16x16(128_dc, 8, rvv_vl128)
+PRED16x16(128_dc, 8, rvv_vl256)
+PRED16x16(left_dc, 8, rvv_vl128)
+PRED16x16(left_dc, 8, rvv_vl256)
+PRED16x16(top_dc, 8, rvv_vl128)
+PRED16x16(top_dc, 8, rvv_vl256)
+PRED16x16(plane, 8, rvv_vl128)
+PRED16x16(plane, 8, rvv_vl256)
+
+av_cold void ff_h264_pred_init_riscv(H264PredContext *h, int codec_id,
+ const int bit_depth,
+ const int chroma_format_idc)
+{
+#if HAVE_RVV
+ int cpu_flags = av_get_cpu_flags();
+
+ if (!(cpu_flags & AV_CPU_FLAG_RVV_I32) || !ff_rv_vlen_least(128)) return;
+
+ const int vlen = 8 * ff_get_rv_vlenb();
+
+ if (bit_depth == 8) {
+ if (chroma_format_idc <= 1) {
+ if (codec_id != AV_CODEC_ID_VP7 && codec_id != AV_CODEC_ID_VP8 &&
+ (cpu_flags & AV_CPU_FLAG_RVB)) {
+ if (vlen >= 256) {
+ h->pred8x8[PLANE_PRED8x8] = ff_pred8x8_plane_8_rvv_vl256;
+ } else {
+ h->pred8x8[PLANE_PRED8x8] = ff_pred8x8_plane_8_rvv_vl128;
+ }
+ }
+ if (vlen >= 256) {
+ h->pred8x8[HOR_PRED8x8] = ff_pred8x8_horizontal_8_rvv_vl256;
+ } else {
+ h->pred8x8[HOR_PRED8x8] = ff_pred8x8_horizontal_8_rvv_vl128;
+ }
+ }
+ if (vlen >= 256) {
+ h->pred16x16[HOR_PRED8x8] = ff_pred16x16_horizontal_8_rvv_vl256;
+ h->pred16x16[DC_PRED8x8] = ff_pred16x16_dc_8_rvv_vl256;
+ h->pred16x16[LEFT_DC_PRED8x8] = ff_pred16x16_left_dc_8_rvv_vl256;
+ if (cpu_flags & AV_CPU_FLAG_RVB)
+ h->pred16x16[TOP_DC_PRED8x8] = ff_pred16x16_top_dc_8_rvv_vl256;
+ h->pred16x16[VERT_PRED8x8] = ff_pred16x16_vertical_8_rvv_vl256;
+ h->pred16x16[DC_128_PRED8x8] = ff_pred16x16_128_dc_8_rvv_vl256;
+ } else {
+ h->pred16x16[HOR_PRED8x8] = ff_pred16x16_horizontal_8_rvv_vl128;
+ h->pred16x16[DC_PRED8x8] = ff_pred16x16_dc_8_rvv_vl128;
+ h->pred16x16[LEFT_DC_PRED8x8] = ff_pred16x16_left_dc_8_rvv_vl128;
+ if (cpu_flags & AV_CPU_FLAG_RVB)
+ h->pred16x16[TOP_DC_PRED8x8] = ff_pred16x16_top_dc_8_rvv_vl128;
+ h->pred16x16[VERT_PRED8x8] = ff_pred16x16_vertical_8_rvv_vl128;
+ h->pred16x16[DC_128_PRED8x8] = ff_pred16x16_128_dc_8_rvv_vl128;
+ }
+ if (codec_id != AV_CODEC_ID_SVQ3 && codec_id != AV_CODEC_ID_RV40 &&
+ codec_id != AV_CODEC_ID_VP7 && codec_id != AV_CODEC_ID_VP8 &&
+ (cpu_flags & AV_CPU_FLAG_RVB)) {
+ if (vlen >= 256) {
+ h->pred16x16[PLANE_PRED8x8] = ff_pred16x16_plane_8_rvv_vl256;
+ } else {
+ h->pred16x16[PLANE_PRED8x8] = ff_pred16x16_plane_8_rvv_vl128;
+ }
+ }
+ }
+#endif
+}
diff --git a/libavcodec/riscv/h264_intrapred_rvv.S
b/libavcodec/riscv/h264_intrapred_rvv.S
new file mode 100644
index 0000000000..5f3bd0d992
--- /dev/null
+++ b/libavcodec/riscv/h264_intrapred_rvv.S
@@ -0,0 +1,679 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright © 2025 Tristan Matthews
+ * Partly based on h264_pred.c Copyright (c) 2023 SiFive, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "libavutil/riscv/asm.S"
+
+.macro vsetvlstatic8 len vlen lastlen=0
+.if \lastlen == \len
+/* These are for when we don't want to change VL */
+.if \vlen >= 256
+.if \len <= 4
+ vsetvli zero, zero, e8, mf8, ta, ma
+.elseif \len <= 8
+ vsetvli zero, zero, e8, mf4, ta, ma
+.elseif \len <= 16
+ vsetvli zero, zero, e8, mf2, ta, ma
+.elseif \len <= 31
+ vsetvli zero, zero, e8, m1, ta, ma
+.endif
+.else
+.if \len <= 4
+ vsetvli zero, zero, e8, mf4, ta, ma
+.elseif \len <= 8
+ vsetvli zero, zero, e8, mf2, ta, ma
+.elseif \len <= 16
+ vsetvli zero, zero, e8, m1, ta, ma
+.elseif \len <= 31
+ vsetvli zero, zero, e8, m2, ta, ma
+.endif
+.endif
+.else
+.if \vlen >= 256
+.if \len <= 4
+ vsetivli zero, \len, e8, mf8, ta, ma
+.elseif \len <= 8
+ vsetivli zero, \len, e8, mf4, ta, ma
+.elseif \len <= 16
+ vsetivli zero, \len, e8, mf2, ta, ma
+.elseif \len <= 31
+ vsetivli zero, \len, e8, m1, ta, ma
+.endif
+.else
+.if \len <= 4
+ vsetivli zero, \len, e8, mf4, ta, ma
+.elseif \len <= 8
+ vsetivli zero, \len, e8, mf2, ta, ma
+.elseif \len <= 16
+ vsetivli zero, \len, e8, m1, ta, ma
+.elseif \len <= 31
+ vsetivli zero, \len, e8, m2, ta, ma
+.endif
+.endif
+.endif
+.endm
+
+.macro vsetvlstatic16 len vlen lastlen=0
+.if \lastlen == \len
+/* These are for when we don't want to change VL */
+.if \vlen >= 256
+.if \len <= 4
+ vsetvli zero, zero, e16, mf4, ta, ma
+.elseif \len <= 8
+ vsetvli zero, zero, e16, mf2, ta, ma
+.elseif \len <= 16
+ vsetvli zero, zero, e16, m1, ta, ma
+.endif
+.else
+.if \len <= 4
+ vsetvli zero, zero, e16, mf2, ta, ma
+.elseif \len <= 8
+ vsetvli zero, zero, e16, m1, ta, ma
+.elseif \len <= 16
+ vsetvli zero, zero, e16, m2, ta, ma
+.endif
+.endif
+.else
+.if \vlen >= 256
+.if \len <= 4
+ vsetivli zero, \len, e16, mf4, ta, ma
+.elseif \len <= 8
+ vsetivli zero, \len, e16, mf2, ta, ma
+.elseif \len <= 16
+ vsetivli zero, \len, e16, m1, ta, ma
+.endif
+.else
+.if \len <= 4
+ vsetivli zero, \len, e16, mf2, ta, ma
+.elseif \len <= 8
+ vsetivli zero, \len, e16, m1, ta, ma
+.elseif \len <= 16
+ vsetivli zero, \len, e16, m2, ta, ma
+.endif
+.endif
+.endif
+.endm
+
+.macro pred8x8_horizontal_8_rvv vlen
+func ff_pred8x8_horizontal_8_rvv_vl\vlen, zve32x
+ lpad 0
+ vsetvlstatic8 8 \vlen
+
+ addi t0, a0, -1
+ vlse8.v v2, (t0), a1
+
+ mv t0, a0
+ vrgather.vi v0, v2, 0
+ vrgather.vi v1, v2, 1
+ vse8.v v0, (t0)
+ add t0, t0, a1
+ vse8.v v1, (t0)
+ add t0, t0, a1
+ vrgather.vi v0, v2, 2
+ vrgather.vi v1, v2, 3
+ vse8.v v0, (t0)
+ add t0, t0, a1
+ vse8.v v1, (t0)
+ add t0, t0, a1
+ vrgather.vi v0, v2, 4
+ vrgather.vi v1, v2, 5
+ vse8.v v0, (t0)
+ add t0, t0, a1
+ vse8.v v1, (t0)
+ add t0, t0, a1
+ vrgather.vi v0, v2, 6
+ vrgather.vi v1, v2, 7
+ vse8.v v0, (t0)
+ add t0, t0, a1
+ vse8.v v1, (t0)
+
+ ret
+endfunc
+.endm
+
+pred8x8_horizontal_8_rvv 256
+pred8x8_horizontal_8_rvv 128
+
+.macro pred8x8_plane_8_rvv vlen
+func ff_pred8x8_plane_8_rvv_vl\vlen, zve32x, zba
+ lpad 0
+
+ vsetvlstatic16 8 \vlen
+
+ vid.v v4
+
+ vsetvlstatic8 4 \vlen 8
+
+ sub t0, a0, a1
+ addi t1, t0, 4
+ vle8.v v8, (t1)
+
+ addi t2, t0, -1
+
+ li t3, -1
+ addi t4, t2, 3
+ vlse8.v v10, (t4), t3 # load in reverse order
+
+ slli t3, a1, 2
+ addi t4, t3, -1
+ add t5, a0, t4
+
+ vlse8.v v11, (t5), a1
+ neg a2, a1 # a2 = -stride
+ sh1add t4, a1, a1 # t4 = 3*stride
+ add t4, t2, t4
+ vlse8.v v13, (t4), a2 # load in reverse order
+
+ vwsubu.vv v18, v8, v10
+ vwsubu.vv v20, v11, v13
+
+ vsetvlstatic16 4 \vlen 4
+
+ vmadd.vv v18, v4, v18
+
+ vmadd.vv v20, v4, v20
+
+ vmv.s.x v22, zero
+ vwredsum.vs v22, v20, v22
+
+ vmv.s.x v23, zero
+ vwredsum.vs v23, v18, v23
+
+ vmv.x.s t6, v23
+ slli t1, t6, 4
+ add t6, t6, t1
+ addi t6, t6, 16
+ srai t6, t6, 5
+
+ vmv.x.s t5, v22
+ slli t1, t5, 4
+ add t5, t5, t1
+ addi t5, t5, 16
+ srai t5, t5, 5
+
+ add t2, t6, t5
+ sh1add t3, t2, t2
+
+ slli a2, a1, 3
+ sub a2, a2, a1
+ addi a2, a2, -1
+ add a2, a2, a0
+ lbu a3, (a2)
+
+ addi a2, a0, 7
+ sub a2, a2, a1
+ lbu a4, (a2)
+
+ add a5, a4, a3
+ addi a5, a5, 1
+ slli a5, a5, 4
+
+ sub a5, a5, t3 # linear combination of H, V and
src
+
+ vsetvlstatic16 8 \vlen 4
+
+ vmul.vx v18, v4, t6
+
+ .irp n 19, 20, 21, 22, 23, 24, 25, 26
+ vadd.vx v\n, v18, a5
+ add a5, a5, t5
+ .endr
+
+ .irp n 19, 20, 21, 22, 23, 24, 25, 26
+ vmax.vx v\n, v\n, zero
+ .endr
+
+ .irp n 19, 20, 21, 22, 23, 24, 25, 26
+ vsra.vi v\n, v\n, 5
+ .endr
+
+ vsetvlstatic8 8 \vlen 8
+
+ vnclipu.wi v19, v19, 0
+ vnclipu.wi v20, v20, 0
+ vse8.v v19, (a0)
+ add t1, a0, a1
+ vnclipu.wi v21, v21, 0
+ vse8.v v20, (t1)
+ add t1, t1, a1
+ vnclipu.wi v22, v22, 0
+ vse8.v v21, (t1)
+ add t1, t1, a1
+ vnclipu.wi v23, v23, 0
+ vse8.v v22, (t1)
+ add t1, t1, a1
+ vnclipu.wi v24, v24, 0
+ vse8.v v23, (t1)
+ add t1, t1, a1
+ vnclipu.wi v25, v25, 0
+ vse8.v v24, (t1)
+ add t1, t1, a1
+ vnclipu.wi v26, v26, 0
+ vse8.v v25, (t1)
+ add t1, t1, a1
+ vse8.v v26, (t1)
+
+ ret
+endfunc
+.endm
+
+pred8x8_plane_8_rvv 256
+pred8x8_plane_8_rvv 128
+
+.macro pred16x16_horizontal_8_rvv vlen
+func ff_pred16x16_horizontal_8_rvv_vl\vlen, zve32x
+ lpad 0
+ vsetvlstatic8 16 \vlen
+
+ addi t0, a0, -1
+ vlse8.v v2, (t0), a1
+
+ mv t0, a0
+ vrgather.vi v0, v2, 0
+ vrgather.vi v1, v2, 1
+ vse8.v v0, (t0)
+ add t0, t0, a1
+ vse8.v v1, (t0)
+ add t0, t0, a1
+ vrgather.vi v0, v2, 2
+ vrgather.vi v1, v2, 3
+ vse8.v v0, (t0)
+ add t0, t0, a1
+ vse8.v v1, (t0)
+ add t0, t0, a1
+ vrgather.vi v0, v2, 4
+ vrgather.vi v1, v2, 5
+ vse8.v v0, (t0)
+ add t0, t0, a1
+ vse8.v v1, (t0)
+ add t0, t0, a1
+ vrgather.vi v0, v2, 6
+ vrgather.vi v1, v2, 7
+ vse8.v v0, (t0)
+ add t0, t0, a1
+ vse8.v v1, (t0)
+ add t0, t0, a1
+ vrgather.vi v0, v2, 8
+ vrgather.vi v1, v2, 9
+ vse8.v v0, (t0)
+ add t0, t0, a1
+ vse8.v v1, (t0)
+ add t0, t0, a1
+ vrgather.vi v0, v2, 10
+ vrgather.vi v1, v2, 11
+ vse8.v v0, (t0)
+ add t0, t0, a1
+ vse8.v v1, (t0)
+ add t0, t0, a1
+ vrgather.vi v0, v2, 12
+ vrgather.vi v1, v2, 13
+ vse8.v v0, (t0)
+ add t0, t0, a1
+ vse8.v v1, (t0)
+ add t0, t0, a1
+ vrgather.vi v0, v2, 14
+ vrgather.vi v1, v2, 15
+ vse8.v v0, (t0)
+ add t0, t0, a1
+ vse8.v v1, (t0)
+
+ ret
+endfunc
+.endm
+
+pred16x16_horizontal_8_rvv 256
+pred16x16_horizontal_8_rvv 128
+
+.macro pred16x16_vertical_8_rvv vlen
+func ff_pred16x16_vertical_8_rvv_vl\vlen, zve32x
+ lpad 0
+ vsetvlstatic8 16 \vlen
+
+ sub t0, a0, a1
+
+ vle8.v v0, (t0)
+
+ vse8.v v0, (a0)
+
+ add t1, a0, a1
+ vse8.v v0, (t1)
+
+ .rept 14
+ add t1, t1, a1
+ vse8.v v0, (t1)
+ .endr
+
+ ret
+endfunc
+.endm
+
+pred16x16_vertical_8_rvv 256
+pred16x16_vertical_8_rvv 128
+
+.macro pred16x16_128_dc_8 vlen
+func ff_pred16x16_128_dc_8_rvv_vl\vlen, zve32x
+ lpad 0
+ vsetvlstatic8 16 \vlen
+
+ li t0, 128
+ vmv.v.x v0, t0
+
+ slli a2, a1, 1
+ vse8.v v0, (a0)
+
+ add t2, a0, a1
+ vse8.v v0, (t2)
+
+ add t1, a0, a2
+ add t2, t2, a2
+
+ .rept 6
+ vse8.v v0, (t1)
+ vse8.v v0, (t2)
+
+ add t1, t1, a2
+ add t2, t2, a2
+ .endr
+
+ vse8.v v0, (t1)
+ vse8.v v0, (t2)
+
+ ret
+endfunc
+.endm
+
+pred16x16_128_dc_8 256
+pred16x16_128_dc_8 128
+
+.macro pred16x16_dc_8_rvv vlen
+func ff_pred16x16_dc_8_rvv_vl\vlen, zve32x
+ lpad 0
+ vsetvlstatic16 16 \vlen
+
+ addi t0, a0, -1
+ vlse8.v v0, (t0), a1
+
+ sub t1, a0, a1
+ vle8.v v1, (t1)
+
+ vmv.s.x v2, zero
+
+ vsetvlstatic8 16 \vlen 16
+
+ vwredsumu.vs v2, v0, v2 # sum = sum(left)
+ vwredsumu.vs v2, v1, v2 # sum += sum(top)
+
+ vsetvlstatic16 8 \vlen 16
+
+ li t0, 16
+ vadd.vx v2, v2, t0
+ vsrl.vi v3, v2, 5
+
+ vsetvlstatic8 16 \vlen 8
+
+ vrgather.vi v4, v3, 0
+
+ vse8.v v4, (a0)
+ add t1, a0, a1
+
+ .rept 15
+ vse8.v v4, (t1)
+ add t1, t1, a1
+ .endr
+
+ ret
+endfunc
+.endm
+
+pred16x16_dc_8_rvv 256
+pred16x16_dc_8_rvv 128
+
+.macro pred16x16_left_dc_8_rvv vlen
+func ff_pred16x16_left_dc_8_rvv_vl\vlen, zve32x
+ lpad 0
+ vsetvlstatic16 16 \vlen
+
+ addi t2, a0, -1
+ vlse8.v v1, (t2), a1
+
+ vmv.s.x v2, zero
+
+ vsetvlstatic8 16 \vlen 16
+ vwredsumu.vs v2, v1, v2
+
+ vsetvlstatic16 8 \vlen 16
+
+ vadd.vi v2, v2, 8
+ vsrl.vi v3, v2, 4
+
+ vsetvlstatic8 16 \vlen 8
+
+ vrgather.vi v4, v3, 0
+
+ slli a2, a1, 1
+ add t4, a0, a1
+
+ vse8.v v4, (a0)
+ vse8.v v4, (t4)
+ add t1, a0, a2
+ add t4, t4, a2
+
+ .rept 6
+ vse8.v v4, (t1)
+ vse8.v v4, (t4)
+ add t1, t1, a2
+ add t4, t4, a2
+ .endr
+
+ vse8.v v4, (t1)
+ vse8.v v4, (t4)
+
+ ret
+endfunc
+.endm
+
+pred16x16_left_dc_8_rvv 256
+pred16x16_left_dc_8_rvv 128
+
+.macro pred16x16_top_dc_8_rvv vlen
+func ff_pred16x16_top_dc_8_rvv_vl\vlen, zve32x, zba
+ lpad 0
+ vsetvlstatic16 16 \vlen
+
+ sub t0, a0, a1
+ vle8.v v0, (t0)
+
+ vmv.s.x v1, zero
+
+ vsetvlstatic8 16 \vlen 16
+
+ vwredsumu.vs v1, v0, v1
+
+ vsetvlstatic16 8 \vlen 16
+
+ vadd.vi v1, v1, 8
+ vsrl.vi v1, v1, 4
+
+ vsetvlstatic8 16 \vlen 8
+
+ vrgather.vi v2, v1, 0
+
+ vse8.v v2, (a0)
+ sh1add t1, a1, a0
+ add t2, a0, a1
+ vse8.v v2, (t2)
+
+ sh1add t2, a1, t2
+ vse8.v v2, (t1)
+ vse8.v v2, (t2)
+
+ .rept 6
+ sh1add t1, a1, t1
+ sh1add t2, a1, t2
+ vse8.v v2, (t1)
+ vse8.v v2, (t2)
+ .endr
+
+ ret
+endfunc
+.endm
+
+pred16x16_top_dc_8_rvv 256
+pred16x16_top_dc_8_rvv 128
+
+.macro pred16x16_plane_8_rvv vlen
+func ff_pred16x16_plane_8_rvv_vl\vlen, zve32x, zba
+ lpad 0
+
+ vsetvlstatic8 8 \vlen
+
+ sub t0, a0, a1
+ addi t1, t0, 8
+ addi t2, t0, -1
+ li t3, -1
+ vle8.v v3, (t1)
+ add t4, t2, 7
+ vlse8.v v5, (t4), t3
+
+ sh3add t3, a1, a0
+ addi t3, t3, -1
+
+ vlse8.v v6, (t3), a1
+
+ neg a2, a1
+ sh3add t4, a1, a2 # t4 = 7*stride
+ add t5, t2, t4
+ vlse8.v v8, (t5), a2 # load in reverse order
+
+ vwsubu.vv v13, v3, v5
+ vwsubu.vv v16, v6, v8
+
+ vsetvlstatic16 16 \vlen 8
+
+ vid.v v14
+
+ vsetvlstatic16 8 \vlen 16
+
+ vmadd.vv v13, v14, v13
+
+ vmadd.vv v16, v14, v16
+
+ vmv.s.x v18, zero
+ vwredsum.vs v18, v16, v18
+
+ vmv.s.x v19, zero
+ vwredsum.vs v19, v13, v19
+
+ vmv.x.s t4, v19
+ sh2add t1, t4, t4
+ addi t1, t1, 32
+ srai t1, t1, 6
+
+ vmv.x.s t5, v18
+ sh2add t2, t5, t5
+ addi t2, t2, 32
+ srai t2, t2, 6
+
+ add t3, t1, t2
+ slli t4, t3, 3
+ sub t4, t4, t3
+
+ slli t5, a1, 4
+ sub t5, t5, a1
+ addi t5, t5, -1
+
+ sub t6, a0, a1
+ addi t6, t6, 15
+ lbu a2, (t6)
+
+ add a3, a0, t5
+ lbu a4, (a3)
+
+ add a4, a4, a2
+ addi a4, a4, 1
+ slli a4, a4, 4
+
+ sub a5, a4, t4 # a5 = linear combination of H, V
and src
+
+ vsetvlstatic16 16 \vlen 8
+
+ vmul.vx v24, v14, t1
+
+ mv t3, a0
+
+ .rept 2
+
+ vsetvlstatic16 16 \vlen 16
+
+ .irp n 2, 4, 6, 8, 10, 12, 14, 16
+ vadd.vx v\n, v24, a5
+ add a5, a5, t2
+ .endr
+
+ .irp n, 2, 4, 6, 8, 10, 12, 14, 16
+ vmax.vx v\n, v\n, zero
+ .endr
+
+ .irp n, 2, 4, 6, 8, 10, 12, 14, 16
+ vsra.vi v\n, v\n, 5
+ .endr
+
+ vsetvlstatic8 16 \vlen 16
+
+ vnclipu.wi v2, v2, 0
+ vnclipu.wi v4, v4, 0
+ vse8.v v2, (t3)
+ add t3, t3, a1
+ vnclipu.wi v6, v6, 0
+ vse8.v v4, (t3)
+ add t3, t3, a1
+ vnclipu.wi v8, v8, 0
+ vse8.v v6, (t3)
+ add t3, t3, a1
+ vnclipu.wi v10, v10, 0
+ vse8.v v8, (t3)
+ add t3, t3, a1
+ vnclipu.wi v12, v12, 0
+ vse8.v v10, (t3)
+ add t3, t3, a1
+ vnclipu.wi v14, v14, 0
+ vse8.v v12, (t3)
+ add t3, t3, a1
+ vnclipu.wi v16, v16, 0
+ vse8.v v14, (t3)
+ add t3, t3, a1
+ vse8.v v16, (t3)
+ add t3, t3, a1
+ .endr
+
+ ret
+endfunc
+.endm
+
+pred16x16_plane_8_rvv 256
+pred16x16_plane_8_rvv 128
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