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commit d64b47f2596e2458c8c34559593cc14bc3c87407 Author: Shreesh Adiga <[email protected]> AuthorDate: Fri Jul 10 20:05:15 2026 +0530 Commit: Martin Storsjö <[email protected]> CommitDate: Wed Sep 16 06:29:59 2026 +0000 avutil/cpu: add aarch64 CPU feature flag for ARM AES --- configure | 7 ++++++- libavutil/aarch64/asm.S | 9 +++++++-- libavutil/aarch64/cpu.c | 12 +++++++++++- libavutil/aarch64/cpu.h | 1 + libavutil/cpu.c | 1 + libavutil/cpu.h | 1 + libavutil/tests/cpu.c | 1 + tests/checkasm/checkasm.c | 1 + 8 files changed, 29 insertions(+), 4 deletions(-) diff --git a/configure b/configure index 046a0bd005..7ea67ef558 100755 --- a/configure +++ b/configure @@ -478,6 +478,7 @@ Optimization options (experts only): --disable-armv6t2 disable armv6t2 optimizations --disable-vfp disable VFP optimizations --disable-neon disable NEON optimizations + --disable-arm-aes disable ARM/AArch64 AES optimizations --disable-arm-crc disable ARM/AArch64 CRC optimizations --disable-dotprod disable DOTPROD optimizations --disable-i8mm disable I8MM optimizations @@ -2320,6 +2321,7 @@ ARCH_EXT_LIST_ARM=" armv6 armv6t2 armv8 + arm_aes arm_crc dotprod i8mm @@ -2922,6 +2924,7 @@ intrinsics_sse2_deps="sse2" vfp_deps="arm" vfpv3_deps="vfp" setend_deps="arm" +arm_aes_deps="aarch64 neon" arm_crc_deps="aarch64" dotprod_deps="aarch64 neon" i8mm_deps="aarch64 neon" @@ -6527,7 +6530,8 @@ if enabled aarch64; then # internal assembler in clang 3.3 does not support this instruction enabled neon && check_insn neon 'ext v0.8B, v0.8B, v1.8B, #1' - archext_list="arm_crc dotprod i8mm pmull eor3 sve sve2 sme sme_i16i64 sme2" + archext_list="arm_aes arm_crc dotprod i8mm pmull eor3 sve sve2 sme sme_i16i64 sme2" + enabled arm_aes && check_archext_name_insn arm_aes aes 'aese v0.16b, v1.16b' enabled arm_crc && check_archext_name_insn arm_crc crc 'crc32x w0, w0, x0' enabled pmull && check_archext_name_insn pmull aes 'pmull v0.1q, v0.1d, v0.1d' enabled eor3 && check_archext_name_insn eor3 sha3 'eor3 v0.16b, v1.16b, v2.16b, v3.16b' @@ -8312,6 +8316,7 @@ if enabled aarch64; then echo "NEON enabled ${neon-no}" echo "DOTPROD enabled ${dotprod-no}" echo "I8MM enabled ${i8mm-no}" + echo "ARM_AES enabled ${arm_aes-no}" echo "PMULL enabled ${pmull-no}" echo "EOR3 enabled ${eor3-no}" echo "SVE enabled ${sve-no}" diff --git a/libavutil/aarch64/asm.S b/libavutil/aarch64/asm.S index e0cb74a579..665202a808 100644 --- a/libavutil/aarch64/asm.S +++ b/libavutil/aarch64/asm.S @@ -65,10 +65,14 @@ #endif #if HAVE_AS_ARCHEXT_AES_DIRECTIVE -#define ENABLE_PMULL .arch_extension aes -#define DISABLE_PMULL .arch_extension noaes +#define ENABLE_ARM_AES .arch_extension aes +#define ENABLE_PMULL .arch_extension aes +#define DISABLE_ARM_AES .arch_extension noaes +#define DISABLE_PMULL .arch_extension noaes #else +#define ENABLE_ARM_AES #define ENABLE_PMULL +#define DISABLE_ARM_AES #define DISABLE_PMULL #endif @@ -121,6 +125,7 @@ #endif DISABLE_ARM_CRC +DISABLE_ARM_AES DISABLE_PMULL DISABLE_EOR3 DISABLE_DOTPROD diff --git a/libavutil/aarch64/cpu.c b/libavutil/aarch64/cpu.c index b8d2bd3280..40e82a1c55 100644 --- a/libavutil/aarch64/cpu.c +++ b/libavutil/aarch64/cpu.c @@ -24,6 +24,7 @@ #include <stdint.h> #include <sys/auxv.h> +#define HWCAP_AARCH64_AES (1 << 3) #define HWCAP_AARCH64_PMULL (1 << 4) #define HWCAP_AARCH64_CRC32 (1 << 7) #define HWCAP_AARCH64_SHA3 (1 << 17) @@ -42,6 +43,8 @@ static int detect_flags(void) unsigned long hwcap = ff_getauxval(AT_HWCAP); unsigned long hwcap2 = ff_getauxval(AT_HWCAP2); + if (hwcap & HWCAP_AARCH64_AES) + flags |= AV_CPU_FLAG_ARM_AES; if (hwcap & HWCAP_AARCH64_PMULL) flags |= AV_CPU_FLAG_PMULL; if (hwcap & HWCAP_AARCH64_SHA3) @@ -91,6 +94,8 @@ static int detect_flags(void) flags |= AV_CPU_FLAG_SME_I16I64; if (have_feature("hw.optional.armv8_crc32")) flags |= AV_CPU_FLAG_ARM_CRC; + if (have_feature("hw.optional.arm.FEAT_AES")) + flags |= AV_CPU_FLAG_ARM_AES; if (have_feature("hw.optional.arm.FEAT_PMULL")) flags |= AV_CPU_FLAG_PMULL; if (have_feature("hw.optional.armv8_2_sha3")) @@ -125,6 +130,8 @@ static int detect_flags(void) flags |= AV_CPU_FLAG_DOTPROD; if (ID_AA64ISAR0_CRC32(isar0) >= ID_AA64ISAR0_CRC32_BASE) flags |= AV_CPU_FLAG_ARM_CRC; + if (ID_AA64ISAR0_AES(isar0) >= ID_AA64ISAR0_AES_BASE) + flags |= AV_CPU_FLAG_ARM_AES; if (ID_AA64ISAR0_AES(isar0) >= ID_AA64ISAR0_AES_PMULL) flags |= AV_CPU_FLAG_PMULL; if (ID_AA64ISAR0_SHA3(isar0) >= ID_AA64ISAR0_SHA3_IMPL) @@ -156,8 +163,10 @@ static int detect_flags(void) flags |= AV_CPU_FLAG_ARM_CRC; #endif #ifdef PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE - if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) + if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) { + flags |= AV_CPU_FLAG_ARM_AES; flags |= AV_CPU_FLAG_PMULL; + } #endif #ifdef PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE if (IsProcessorFeaturePresent(PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE)) @@ -226,6 +235,7 @@ int ff_get_cpu_flags_aarch64(void) flags |= AV_CPU_FLAG_ARM_CRC; #endif #ifdef __ARM_FEATURE_AES + flags |= AV_CPU_FLAG_ARM_AES; flags |= AV_CPU_FLAG_PMULL; #endif #ifdef __ARM_FEATURE_SHA3 diff --git a/libavutil/aarch64/cpu.h b/libavutil/aarch64/cpu.h index 433ba60bca..91e5725f57 100644 --- a/libavutil/aarch64/cpu.h +++ b/libavutil/aarch64/cpu.h @@ -26,6 +26,7 @@ #define have_neon(flags) CPUEXT(flags, NEON) #define have_vfp(flags) CPUEXT(flags, VFP) #define have_arm_crc(flags) CPUEXT(flags, ARM_CRC) +#define have_arm_aes(flags) CPUEXT(flags, ARM_AES) #define have_pmull(flags) CPUEXT(flags, PMULL) #define have_eor3(flags) CPUEXT(flags, EOR3) #define have_dotprod(flags) CPUEXT(flags, DOTPROD) diff --git a/libavutil/cpu.c b/libavutil/cpu.c index 00029f81ca..6994166147 100644 --- a/libavutil/cpu.c +++ b/libavutil/cpu.c @@ -193,6 +193,7 @@ int av_parse_cpu_caps(unsigned *flags, const char *s) { "sme2", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SME2 }, .unit = "flags" }, { "pmull", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_PMULL }, .unit = "flags" }, { "eor3", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_EOR3 }, .unit = "flags" }, + { "aes", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ARM_AES }, .unit = "flags" }, #elif ARCH_MIPS { "mmi", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_MMI }, .unit = "flags" }, { "msa", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_MSA }, .unit = "flags" }, diff --git a/libavutil/cpu.h b/libavutil/cpu.h index c41686344f..5db34c2e2a 100644 --- a/libavutil/cpu.h +++ b/libavutil/cpu.h @@ -84,6 +84,7 @@ #define AV_CPU_FLAG_SETEND (1 <<16) #define AV_CPU_FLAG_PMULL (1 <<17) #define AV_CPU_FLAG_EOR3 (1 <<18) +#define AV_CPU_FLAG_ARM_AES (1 <<19) #define AV_CPU_FLAG_MMI (1 << 0) #define AV_CPU_FLAG_MSA (1 << 1) diff --git a/libavutil/tests/cpu.c b/libavutil/tests/cpu.c index f74d02270e..379feffe70 100644 --- a/libavutil/tests/cpu.c +++ b/libavutil/tests/cpu.c @@ -54,6 +54,7 @@ static const struct { { AV_CPU_FLAG_SME2, "sme2" }, { AV_CPU_FLAG_PMULL, "pmull" }, { AV_CPU_FLAG_EOR3, "eor3" }, + { AV_CPU_FLAG_ARM_AES, "aes" }, #elif ARCH_ARM { AV_CPU_FLAG_ARMV5TE, "armv5te" }, { AV_CPU_FLAG_ARMV6, "armv6" }, diff --git a/tests/checkasm/checkasm.c b/tests/checkasm/checkasm.c index b9d7b0d2d4..f0f6f097de 100644 --- a/tests/checkasm/checkasm.c +++ b/tests/checkasm/checkasm.c @@ -333,6 +333,7 @@ static const CheckasmCpuInfo cpuflags[] = { { "SME2", "sme2", AV_CPU_FLAG_SME2 }, { "PMULL", "pmull_eor3", AV_CPU_FLAG_PMULL|AV_CPU_FLAG_EOR3, .mask = AV_CPU_FLAG_ARM_CRC }, { "PMULL+CRC","pmull_eor3_crc", AV_CPU_FLAG_PMULL|AV_CPU_FLAG_EOR3|AV_CPU_FLAG_ARM_CRC }, + { "AES", "aes", AV_CPU_FLAG_ARM_AES }, #elif ARCH_ARM { "ARMV5TE", "armv5te", AV_CPU_FLAG_ARMV5TE }, { "ARMV6", "armv6", AV_CPU_FLAG_ARMV6 }, -- To stop receiving notification emails like this one, please contact [email protected]. _______________________________________________ ffmpeg-cvslog mailing list -- [email protected] To unsubscribe send an email to [email protected]
