> -----原始邮件-----
> 发件人: "Jiaxun Yang" <jiaxun.y...@flygoat.com>
> 发送时间: 2021-07-22 21:59:03 (星期四)
> 收件人: ffmpeg-devel@ffmpeg.org
> 抄送:
> 主题: Re: [FFmpeg-devel] [PATCH v2 2/5] avutil/mips: Extract load store with
shift C1 pair marco
>
>
> 在 2021/7/22 下午7:55, yinshiyou...@loongson.cn 写道:
> > > -----原始邮件-----
> > > 发件人: "Jiaxun Yang" <jiaxun.y...@flygoat.com>
> > > 发送时间: 2021-07-21 17:19:10 (星期三)
> > > 收件人: ffmpeg-devel@ffmpeg.org
> > > 抄送: yinshiyou...@loongson.cn, "Jiaxun Yang"
<jiaxun.y...@flygoat.com>
> > > 主题: [FFmpeg-devel] [PATCH v2 2/5] avutil/mips: Extract load
store with shift C1 pair marco
> > >
> > > We're doing some fancy hacks with load store with shift C1
> > > beside unaligned load store. Create a marco for l/r pair
> > > to allow us use it in these places.
> > >
> > > Signed-off-by: Jiaxun Yang <jiaxun.y...@flygoat.com>
> > > ---
> > > libavutil/mips/mmiutils.h | 49
++++++++++++++++++++++++---------------
> > > 1 file changed, 30 insertions(+), 19 deletions(-)
> > >
> > > diff --git a/libavutil/mips/mmiutils.h
b/libavutil/mips/mmiutils.h
> > > index 41715c6490..f5b600e50c 100644
> > > --- a/libavutil/mips/mmiutils.h
> > > +++ b/libavutil/mips/mmiutils.h
> > > @@ -57,8 +57,9 @@
> > > #define MMI_LWC1(fp, addr, bias)
\
> > > "lwc1 "#fp", "#bias"("#addr")
\n\t"
> > >
> > > -#define MMI_ULWC1(fp, addr, bias)
\
> > > - "ulw %[low32], "#bias"("#addr")
\n\t" \
> > > +#define MMI_LWLRC1(fp, addr, bias, off)
\
> > > + "lwl %[low32], "#bias"+"#off"("#addr")
\n\t" \
> > > + "lwr %[low32], "#bias"("#addr")
\n\t" \
> > > "mtc1 %[low32], "#fp"
\n\t"
> > >
> > > #define MMI_LWXC1(fp, addr, stride, bias)
\
> > > @@ -68,9 +69,10 @@
> > > #define MMI_SWC1(fp, addr, bias)
\
> > > "swc1 "#fp", "#bias"("#addr")
\n\t"
> > >
> > > -#define MMI_USWC1(fp, addr, bias)
\
> > > +#define MMI_SWLRC1(fp, addr, bias, off)
\
> > > "mfc1 %[low32], "#fp"
\n\t" \
> > > - "usw %[low32], "#bias"("#addr")
\n\t"
> > > + "swl %[low32], "#bias"+"#off"("#addr")
\n\t" \
> > > + "swr %[low32], "#bias"("#addr")
\n\t"
> > >
> > > #define MMI_SWXC1(fp, addr, stride, bias)
\
> > > PTR_ADDU "%[addrt], "#addr", "#stride"
\n\t" \
> > > @@ -79,8 +81,9 @@
> > > #define MMI_LDC1(fp, addr, bias)
\
> > > "ldc1 "#fp", "#bias"("#addr")
\n\t"
> > >
> > > -#define MMI_ULDC1(fp, addr, bias)
\
> > > - "uld %[all64], "#bias"("#addr")
\n\t" \
> > > +#define MMI_LDLRC1(fp, addr, bias, off)
\
> > > + "ldl %[all64], "#bias"+"#off"("#addr")
\n\t" \
> > > + "ldr %[all64], "#bias"("#addr")
\n\t" \
> > > "dmtc1 %[all64], "#fp"
\n\t"
> > >
> > > #define MMI_LDXC1(fp, addr, stride, bias)
\
> > > @@ -90,9 +93,10 @@
> > > #define MMI_SDC1(fp, addr, bias)
\
> > > "sdc1 "#fp", "#bias"("#addr")
\n\t"
> > >
> > > -#define MMI_USDC1(fp, addr, bias)
\
> > > +#define MMI_SDLRC1(fp, addr, bias, off)
\
> > > "dmfc1 %[all64], "#fp"
\n\t" \
> > > - "usd %[all64], "#bias"("#addr")
\n\t"
> > > + "sdl %[all64], "#bias"+"#off"("#addr")
\n\t" \
> > > + "sdr %[all64], "#bias"("#addr")
\n\t"
> > >
> > > #define MMI_SDXC1(fp, addr, stride, bias)
\
> > > PTR_ADDU "%[addrt], "#addr", "#stride"
\n\t" \
> > > @@ -141,17 +145,18 @@
> > > #define DECLARE_VAR_LOW32 int32_t low32
> > > #define RESTRICT_ASM_LOW32 [low32]"=&r"(low32),
> > >
> > > -#define MMI_ULWC1(fp, addr, bias)
\
> > > - "ulw %[low32], "#bias"("#addr")
\n\t" \
> > > - "mtc1 %[low32], "#fp"
\n\t"
> > > +#define MMI_LWLRC1(fp, addr, bias, off)
\
> > > + "lwl %[low32], "#bias"+"#off"("#addr")
\n\t" \
> > > + "lwr %[low32], "#bias"("#addr")
\n\t" \
> > > + "mtc1 %[low32], "#fp"
\n\t"
> > >
> > > #else /* _MIPS_SIM != _ABIO32 */
> > >
> > > #define DECLARE_VAR_LOW32
> > > #define RESTRICT_ASM_LOW32
> > >
> > > -#define MMI_ULWC1(fp, addr, bias)
\
> > > - "gslwlc1 "#fp", 3+"#bias"("#addr")
\n\t" \
> > > +#define MMI_LWLRC1(fp, addr, bias, off)
\
> > > + "gslwlc1 "#fp", "#off"+"#bias"("#addr")
\n\t" \
> > > "gslwrc1 "#fp", "#bias"("#addr")
\n\t"
> > >
> > > #endif /* _MIPS_SIM != _ABIO32 */
> > > @@ -162,8 +167,8 @@
> > > #define MMI_SWC1(fp, addr, bias)
\
> > > "swc1 "#fp", "#bias"("#addr")
\n\t"
> > >
> > > -#define MMI_USWC1(fp, addr, bias)
\
> > > - "gsswlc1 "#fp", 3+"#bias"("#addr")
\n\t" \
> > > +#define MMI_SWLRC1(fp, addr, bias, off)
\
> > > + "gsswlc1 "#fp", "#off"+"#bias"("#addr")
\n\t" \
> > > "gsswrc1 "#fp", "#bias"("#addr")
\n\t"
> > >
> > > #define MMI_SWXC1(fp, addr, stride, bias)
\
> > > @@ -172,8 +177,8 @@
> > > #define MMI_LDC1(fp, addr, bias)
\
> > > "ldc1 "#fp", "#bias"("#addr")
\n\t"
> > >
> > > -#define MMI_ULDC1(fp, addr, bias)
\
> > > - "gsldlc1 "#fp", 7+"#bias"("#addr")
\n\t" \
> > > +#define MMI_LDLRC1(fp, addr, bias, off)
\
> > > + "gsldlc1 "#fp", "#off"+"#bias"("#addr")
\n\t" \
> > > "gsldrc1 "#fp", "#bias"("#addr")
\n\t"
> > >
> > > #define MMI_LDXC1(fp, addr, stride, bias)
\
> > > @@ -182,8 +187,8 @@
> > > #define MMI_SDC1(fp, addr, bias)
\
> > > "sdc1 "#fp", "#bias"("#addr")
\n\t"
> > >
> > > -#define MMI_USDC1(fp, addr, bias)
\
> > > - "gssdlc1 "#fp", 7+"#bias"("#addr")
\n\t" \
> > > +#define MMI_SDLRC1(fp, addr, bias, off)
\
> > > + "gssdlc1 "#fp", "#off"+"#bias"("#addr")
\n\t" \
> > > "gssdrc1 "#fp", "#bias"("#addr")
\n\t"
> > >
> > > #define MMI_SDXC1(fp, addr, stride, bias)
\
> > > @@ -203,6 +208,12 @@
> > >
> > > #endif /* HAVE_LOONGSON2 */
> > >
> > > +#define MMI_ULWC1(fp, addr, bias) MMI_LWLRC1(fp, addr, bias, 3)
> > > +#define MMI_USWC1(fp, addr, bias) MMI_SWLRC1(fp, addr, bias, 3)
> > > +
> > > +#define MMI_ULDC1(fp, addr, bias) MMI_LDLRC1(fp, addr, bias, 7)
> > > +#define MMI_USDC1(fp, addr, bias) MMI_SDLRC1(fp, addr, bias, 7)
> > > +
> > > /**
> > > * Backup saved registers
> > > * We're not using compiler's clobber list as it's not smart
enough
> > > --
> > > 2.32.0
> > >
> >
> > 1. Use l/r pair is a good choice.
> > 2. Suggest keep the macro name unchanged, it's easier to use and
associated with unaligned access.
>
> Hmm, the name of {MMI_ULDC1, MMI_USDC1} is actually unchanged, what do
> you meant by macro name?
>
> Thanks.
>
>
For your reference.
