PR #24740 opened by Zhao Zhili (quink)
URL: https://code.ffmpeg.org/FFmpeg/FFmpeg/pulls/24740
Patch URL: https://code.ffmpeg.org/FFmpeg/FFmpeg/pulls/24740.patch
For 71cc3d34a96d5, it's easy to use the following two implementation
```
.macro uni_w_post4 out, in
smull \out\().4s, \in\().4h, v30.4h
sqrshl \out\().4s, \out\().4s, v31.4s
sqadd \out\().4s, \out\().4s, v29.4s
sqxtn \out\().4h, \out\().4s
sqxtun \out\().8b, \out\().8h
.endm
.macro uni_w_post8 out, in, t
smull \out\().4s, \in\().4h, v30.4h
smull2 \t\().4s, \in\().8h, v30.8h
sqrshl \out\().4s, \out\().4s, v31.4s
sqrshl \t\().4s, \t\().4s, v31.4s
sqadd \out\().4s, \out\().4s, v29.4s
sqadd \t\().4s, \t\().4s, v29.4s
sqxtn \out\().4h, \out\().4s
sqxtn2 \out\().8h, \t\().4s
sqxtun \out\().8b, \out\().8h
.endm
```
There is no big loss and has some small gain on out-of-order cores, but got 10%
to 20% loss for in-order core (Cortex A510).
So a complex strategy is used to preserve the effect of manual ordering.
>From 60755b9539122de6607c46d2eed6a1908453f54e Mon Sep 17 00:00:00 2001
From: Zhao Zhili <[email protected]>
Date: Wed, 16 Sep 2026 16:55:30 +0800
Subject: [PATCH 1/2] aarch64/h26x: fold qpel horizontal variant tails into
macros
post_h_2reg and post_h_4reg hold the blend-and-narrow sequence shared by
the qpel_uni and qpel_bi width wrappers.
---
libavcodec/aarch64/h26x/qpel_epilogue_neon.S | 51 +++++++++++
libavcodec/aarch64/h26x/qpel_neon.S | 95 ++------------------
2 files changed, 60 insertions(+), 86 deletions(-)
create mode 100644 libavcodec/aarch64/h26x/qpel_epilogue_neon.S
diff --git a/libavcodec/aarch64/h26x/qpel_epilogue_neon.S
b/libavcodec/aarch64/h26x/qpel_epilogue_neon.S
new file mode 100644
index 0000000000..3f7712d439
--- /dev/null
+++ b/libavcodec/aarch64/h26x/qpel_epilogue_neon.S
@@ -0,0 +1,51 @@
+/*
+ * This file is part of FFmpeg.
+ *
+ * FFmpeg is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * FFmpeg is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with FFmpeg; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Blend-and-narrow tails shared by the qpel_uni and qpel_bi horizontal
+ * filters. esz is the number of lanes blended.
+ */
+.macro post_h_2reg type, esz, r0, r1, s0, s1
+.ifc \type, qpel_bi
+ sqadd \r0\().\esz\()h, \r0\().\esz\()h, \s0\().\esz\()h
+ sqadd \r1\().\esz\()h, \r1\().\esz\()h, \s1\().\esz\()h
+ sqrshrun \r0\().8b, \r0\().8h, #7
+ sqrshrun \r1\().8b, \r1\().8h, #7
+.else
+ sqrshrun \r0\().8b, \r0\().8h, #6
+ sqrshrun \r1\().8b, \r1\().8h, #6
+.endif
+.endm
+
+.macro post_h_4reg type, r0, r1, r2, r3, s0, s1, s2, s3
+.ifc \type, qpel_bi
+ sqadd \r0\().8h, \r0\().8h, \s0\().8h
+ sqadd \r1\().8h, \r1\().8h, \s1\().8h
+ sqadd \r2\().8h, \r2\().8h, \s2\().8h
+ sqadd \r3\().8h, \r3\().8h, \s3\().8h
+ sqrshrun \r0\().8b, \r0\().8h, #7
+ sqrshrun \r1\().8b, \r1\().8h, #7
+ sqrshrun \r2\().8b, \r2\().8h, #7
+ sqrshrun \r3\().8b, \r3\().8h, #7
+.else
+ sqrshrun \r0\().8b, \r0\().8h, #6
+ sqrshrun \r1\().8b, \r1\().8h, #6
+ sqrshrun \r2\().8b, \r2\().8h, #6
+ sqrshrun \r3\().8b, \r3\().8h, #6
+.endif
+.endm
diff --git a/libavcodec/aarch64/h26x/qpel_neon.S
b/libavcodec/aarch64/h26x/qpel_neon.S
index 25925665dc..5daf25c46c 100644
--- a/libavcodec/aarch64/h26x/qpel_neon.S
+++ b/libavcodec/aarch64/h26x/qpel_neon.S
@@ -21,6 +21,7 @@
*/
#include "libavutil/aarch64/asm.S"
+#include "qpel_epilogue_neon.S"
#define HEVC_MAX_PB_SIZE 64
#define VVC_MAX_PB_SIZE 128
@@ -281,15 +282,7 @@ function ff_hevc_put_hevc_\type\()_h4_8_neon, export=1
st1 {v23.4h}, [dst], x14
st1 {v24.4h}, [x10], x14
.else
-.ifc \type, qpel_bi
- sqadd v23.4h, v23.4h, v25.4h
- sqadd v24.4h, v24.4h, v26.4h
- sqrshrun v23.8b, v23.8h, #7
- sqrshrun v24.8b, v24.8h, #7
-.else
- sqrshrun v23.8b, v23.8h, #6
- sqrshrun v24.8b, v24.8h, #6
-.endif
+ post_h_2reg \type, 4, v23, v24, v25, v26
st1 {v23.s}[0], [dst], x14
st1 {v24.s}[0], [x10], x14
.endif
@@ -352,15 +345,7 @@ function ff_hevc_put_hevc_\type\()_h6_8_neon, export=1
st1 {v23.s}[2], [dst], x14
st1 {v24.s}[2], [x10], x14
.else
-.ifc \type, qpel_bi
- sqadd v23.8h, v23.8h, v25.8h
- sqadd v24.8h, v24.8h, v26.8h
- sqrshrun v23.8b, v23.8h, #7
- sqrshrun v24.8b, v24.8h, #7
-.else
- sqrshrun v23.8b, v23.8h, #6
- sqrshrun v24.8b, v24.8h, #6
-.endif
+ post_h_2reg \type, 8, v23, v24, v25, v26
st1 {v23.s}[0], [dst], #4
st1 {v24.s}[0], [x10], #4
st1 {v23.h}[2], [dst], x14
@@ -420,15 +405,7 @@ function ff_hevc_put_hevc_\type\()_h8_8_neon, export=1
st1 {v23.8h}, [dst], x14
st1 {v24.8h}, [x10], x14
.else
-.ifc \type, qpel_bi
- sqadd v23.8h, v23.8h, v25.8h
- sqadd v24.8h, v24.8h, v26.8h
- sqrshrun v23.8b, v23.8h, #7
- sqrshrun v24.8b, v24.8h, #7
-.else
- sqrshrun v23.8b, v23.8h, #6
- sqrshrun v24.8b, v24.8h, #6
-.endif
+ post_h_2reg \type, 8, v23, v24, v25, v26
st1 {v23.8b}, [dst], x14
st1 {v24.8b}, [x10], x14
.endif
@@ -505,20 +482,8 @@ function ff_hevc_put_hevc_\type\()_h12_8_neon, export=1
.ifc \type, qpel_bi
ld1 {v16.8h, v17.8h}, [ x4], x16
ld1 {v18.8h, v19.8h}, [x15], x16
- sqadd v26.8h, v26.8h, v16.8h
- sqadd v27.8h, v27.8h, v17.8h
- sqadd v28.8h, v28.8h, v18.8h
- sqadd v29.8h, v29.8h, v19.8h
- sqrshrun v26.8b, v26.8h, #7
- sqrshrun v27.8b, v27.8h, #7
- sqrshrun v28.8b, v28.8h, #7
- sqrshrun v29.8b, v29.8h, #7
-.else
- sqrshrun v26.8b, v26.8h, #6
- sqrshrun v27.8b, v27.8h, #6
- sqrshrun v28.8b, v28.8h, #6
- sqrshrun v29.8b, v29.8h, #6
.endif
+ post_h_4reg \type, v26, v27, v28, v29, v16, v17, v18, v19
st1 {v26.8b}, [dst], #8
st1 {v28.8b}, [x10], #8
st1 {v27.s}[0], [dst], x14
@@ -650,20 +615,8 @@ function ff_hevc_put_hevc_\type\()_h24_8_neon, export=1
.ifc \type, qpel_bi
ld1 {v16.8h, v17.8h}, [ x4], x16
ld1 {v18.8h, v19.8h}, [x15], x16
- sqadd v26.8h, v26.8h, v16.8h
- sqadd v27.8h, v27.8h, v17.8h
- sqadd v28.8h, v28.8h, v18.8h
- sqadd v29.8h, v29.8h, v19.8h
- sqrshrun v26.8b, v26.8h, #7
- sqrshrun v27.8b, v27.8h, #7
- sqrshrun v28.8b, v28.8h, #7
- sqrshrun v29.8b, v29.8h, #7
-.else
- sqrshrun v26.8b, v26.8h, #6
- sqrshrun v27.8b, v27.8h, #6
- sqrshrun v28.8b, v28.8h, #6
- sqrshrun v29.8b, v29.8h, #6
.endif
+ post_h_4reg \type, v26, v27, v28, v29, v16, v17, v18, v19
st1 {v26.8b, v27.8b}, [dst], #16
st1 {v28.8b, v29.8b}, [x10], #16
.endif
@@ -685,14 +638,8 @@ function ff_hevc_put_hevc_\type\()_h24_8_neon, export=1
ld1 {v26.8h}, [x15], x16
sub x4, x4, #48
sub x15, x15, #48
- sqadd v23.8h, v23.8h, v25.8h
- sqadd v24.8h, v24.8h, v26.8h
- sqrshrun v23.8b, v23.8h, #7
- sqrshrun v24.8b, v24.8h, #7
-.else
- sqrshrun v23.8b, v23.8h, #6
- sqrshrun v24.8b, v24.8h, #6
.endif
+ post_h_2reg \type, 8, v23, v24, v25, v26
st1 {v23.8b}, [dst], x14
st1 {v24.8b}, [x10], x14
.endif
@@ -752,20 +699,8 @@ function ff_hevc_put_hevc_\type\()_h16_8_neon, export=1
.ifc \type, qpel_bi
ld1 {v16.8h, v17.8h}, [ x4], x16
ld1 {v18.8h, v19.8h}, [x15], x16
- sqadd v26.8h, v26.8h, v16.8h
- sqadd v27.8h, v27.8h, v17.8h
- sqadd v28.8h, v28.8h, v18.8h
- sqadd v29.8h, v29.8h, v19.8h
- sqrshrun v26.8b, v26.8h, #7
- sqrshrun v27.8b, v27.8h, #7
- sqrshrun v28.8b, v28.8h, #7
- sqrshrun v29.8b, v29.8h, #7
-.else
- sqrshrun v26.8b, v26.8h, #6
- sqrshrun v27.8b, v27.8h, #6
- sqrshrun v28.8b, v28.8h, #6
- sqrshrun v29.8b, v29.8h, #6
.endif
+ post_h_4reg \type, v26, v27, v28, v29, v16, v17, v18, v19
st1 {v26.8b, v27.8b}, [dst], x14
st1 {v28.8b, v29.8b}, [x10], x14
b.gt 1b // double line
@@ -899,20 +834,8 @@ function ff_hevc_put_hevc_\type\()_h32_8_neon, export=1
.ifc \type, qpel_bi
ld1 {v20.8h, v21.8h}, [ x4], #32
ld1 {v22.8h, v23.8h}, [x15], #32
- sqadd v26.8h, v26.8h, v20.8h
- sqadd v27.8h, v27.8h, v21.8h
- sqadd v28.8h, v28.8h, v22.8h
- sqadd v29.8h, v29.8h, v23.8h
- sqrshrun v26.8b, v26.8h, #7
- sqrshrun v27.8b, v27.8h, #7
- sqrshrun v28.8b, v28.8h, #7
- sqrshrun v29.8b, v29.8h, #7
-.else
- sqrshrun v26.8b, v26.8h, #6
- sqrshrun v27.8b, v27.8h, #6
- sqrshrun v28.8b, v28.8h, #6
- sqrshrun v29.8b, v29.8h, #6
.endif
+ post_h_4reg \type, v26, v27, v28, v29, v20, v21, v22, v23
st1 {v26.8b, v27.8b}, [dst], #16
st1 {v28.8b, v29.8b}, [x10], #16
b.gt 1b // double line
--
2.52.0
>From 71cc3d34a96d54bb06651e0efe358ab23c72914f Mon Sep 17 00:00:00 2001
From: Zhao Zhili <[email protected]>
Date: Wed, 16 Sep 2026 18:21:05 +0800
Subject: [PATCH 2/2] aarch64/h26x: share the qpel_uni_w narrowing across
widths
The weighted narrowing after the horizontal filter was repeated at every
width. Sharing one stage at a time rather than a whole block at a time
keeps the serial sqxtn/sqxtn2/sqxtun chain of a block from stalling an
in-order core.
Signed-off-by: Zhao Zhili <[email protected]>
---
libavcodec/aarch64/h26x/qpel_epilogue_neon.S | 51 +++++++++
libavcodec/aarch64/h26x/qpel_neon.S | 107 ++-----------------
2 files changed, 58 insertions(+), 100 deletions(-)
diff --git a/libavcodec/aarch64/h26x/qpel_epilogue_neon.S
b/libavcodec/aarch64/h26x/qpel_epilogue_neon.S
index 3f7712d439..0c68c8ad03 100644
--- a/libavcodec/aarch64/h26x/qpel_epilogue_neon.S
+++ b/libavcodec/aarch64/h26x/qpel_epilogue_neon.S
@@ -16,6 +16,57 @@
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
+.macro uni_w_mul o, i, t
+ smull \o\().4s, \i\().4h, v30.4h
+.ifnb \t
+ smull2 \t\().4s, \i\().8h, v30.8h
+.endif
+.endm
+
+.macro uni_w_shift o, i, t
+ sqrshl \o\().4s, \o\().4s, v31.4s
+.ifnb \t
+ sqrshl \t\().4s, \t\().4s, v31.4s
+.endif
+.endm
+
+.macro uni_w_off o, i, t
+ sqadd \o\().4s, \o\().4s, v29.4s
+.ifnb \t
+ sqadd \t\().4s, \t\().4s, v29.4s
+.endif
+.endm
+
+.macro uni_w_n16 o, i, t
+ sqxtn \o\().4h, \o\().4s
+.ifnb \t
+ sqxtn2 \o\().8h, \t\().4s
+.endif
+.endm
+
+.macro uni_w_n8 o, i, t
+ sqxtun \o\().8b, \o\().8h
+.endm
+
+/* Run one stage over every block of a row. */
+.macro uni_w_stage op, o0, i0, t0, o1, i1, t1, o2, i2, t2
+ \op \o0, \i0, \t0
+.ifnb \o1
+ \op \o1, \i1, \t1
+.endif
+.ifnb \o2
+ \op \o2, \i2, \t2
+.endif
+.endm
+
+.macro uni_w_post o0, i0, t0, o1, i1, t1, o2, i2, t2
+ uni_w_stage uni_w_mul, \o0, \i0, \t0, \o1, \i1, \t1, \o2, \i2,
\t2
+ uni_w_stage uni_w_shift, \o0, \i0, \t0, \o1, \i1, \t1, \o2, \i2,
\t2
+ uni_w_stage uni_w_off, \o0, \i0, \t0, \o1, \i1, \t1, \o2, \i2,
\t2
+ uni_w_stage uni_w_n16, \o0, \i0, \t0, \o1, \i1, \t1, \o2, \i2,
\t2
+ uni_w_stage uni_w_n8, \o0, \i0, \t0, \o1, \i1, \t1, \o2, \i2,
\t2
+.endm
+
/*
* Blend-and-narrow tails shared by the qpel_uni and qpel_bi horizontal
* filters. esz is the number of lanes blended.
diff --git a/libavcodec/aarch64/h26x/qpel_neon.S
b/libavcodec/aarch64/h26x/qpel_neon.S
index 5daf25c46c..ce7c321597 100644
--- a/libavcodec/aarch64/h26x/qpel_neon.S
+++ b/libavcodec/aarch64/h26x/qpel_neon.S
@@ -3482,11 +3482,7 @@ function ff_hevc_put_hevc_qpel_uni_w_h4_8_neon, export=1
mla v18.4h, v7.4h, v0.h[5]
mla v18.4h, v16.4h, v0.h[6]
mla v18.4h, v17.4h, v0.h[7]
- smull v16.4s, v18.4h, v30.4h
- sqrshl v16.4s, v16.4s, v31.4s
- sqadd v16.4s, v16.4s, v29.4s
- sqxtn v16.4h, v16.4s
- sqxtun v16.8b, v16.8h
+ uni_w_post v16, v18
str s16, [x0]
add x0, x0, x1
b.hi 1b
@@ -3517,15 +3513,7 @@ function ff_hevc_put_hevc_qpel_uni_w_h6_8_neon, export=1
mla v18.8h, v7.8h, v0.h[5]
mla v18.8h, v16.8h, v0.h[6]
mla v18.8h, v17.8h, v0.h[7]
- smull v16.4s, v18.4h, v30.4h
- smull2 v17.4s, v18.8h, v30.8h
- sqrshl v16.4s, v16.4s, v31.4s
- sqrshl v17.4s, v17.4s, v31.4s
- sqadd v16.4s, v16.4s, v29.4s
- sqadd v17.4s, v17.4s, v29.4s
- sqxtn v16.4h, v16.4s
- sqxtn2 v16.8h, v17.4s
- sqxtun v16.8b, v16.8h
+ uni_w_post v16, v18, v17
str s16, [x0], #4
st1 {v16.h}[2], [x0], x1
b.hi 1b
@@ -3555,15 +3543,7 @@ function ff_hevc_put_hevc_qpel_uni_w_h8_8_neon, export=1
mla v18.8h, v7.8h, v0.h[5]
mla v18.8h, v16.8h, v0.h[6]
mla v18.8h, v17.8h, v0.h[7]
- smull v16.4s, v18.4h, v30.4h
- smull2 v17.4s, v18.8h, v30.8h
- sqrshl v16.4s, v16.4s, v31.4s
- sqrshl v17.4s, v17.4s, v31.4s
- sqadd v16.4s, v16.4s, v29.4s
- sqadd v17.4s, v17.4s, v29.4s
- sqxtn v16.4h, v16.4s
- sqxtn2 v16.8h, v17.4s
- sqxtun v16.8b, v16.8h
+ uni_w_post v16, v18, v17
st1 {v16.8b}, [x0], x1
b.hi 1b
ret
@@ -3609,20 +3589,7 @@ function ff_hevc_put_hevc_qpel_uni_w_h12_8_neon, export=1
mla v20.4h, v16.4h, v0.h[5]
mla v20.4h, v17.4h, v0.h[6]
mla v20.4h, v18.4h, v0.h[7]
- smull v16.4s, v19.4h, v30.4h
- smull2 v17.4s, v19.8h, v30.8h
- smull v18.4s, v20.4h, v30.4h
- sqrshl v16.4s, v16.4s, v31.4s
- sqrshl v17.4s, v17.4s, v31.4s
- sqrshl v18.4s, v18.4s, v31.4s
- sqadd v16.4s, v16.4s, v29.4s
- sqadd v17.4s, v17.4s, v29.4s
- sqadd v18.4s, v18.4s, v29.4s
- sqxtn v16.4h, v16.4s
- sqxtn2 v16.8h, v17.4s
- sqxtn v17.4h, v18.4s
- sqxtun v16.8b, v16.8h
- sqxtun v17.8b, v17.8h
+ uni_w_post v16, v19, v18, v17, v20
st1 {v16.8b}, [x0], x1
st1 {v17.s}[0], [x13], x1
b.hi 1b
@@ -3668,24 +3635,7 @@ function ff_hevc_put_hevc_qpel_uni_w_h16_8_neon, export=1
mla v20.8h, v16.8h, v0.h[5]
mla v20.8h, v17.8h, v0.h[6]
mla v20.8h, v18.8h, v0.h[7]
- smull v16.4s, v19.4h, v30.4h
- smull2 v17.4s, v19.8h, v30.8h
- smull v18.4s, v20.4h, v30.4h
- smull2 v19.4s, v20.8h, v30.8h
- sqrshl v16.4s, v16.4s, v31.4s
- sqrshl v17.4s, v17.4s, v31.4s
- sqrshl v18.4s, v18.4s, v31.4s
- sqrshl v19.4s, v19.4s, v31.4s
- sqadd v16.4s, v16.4s, v29.4s
- sqadd v17.4s, v17.4s, v29.4s
- sqadd v18.4s, v18.4s, v29.4s
- sqadd v19.4s, v19.4s, v29.4s
- sqxtn v16.4h, v16.4s
- sqxtn2 v16.8h, v17.4s
- sqxtn v17.4h, v18.4s
- sqxtn2 v17.8h, v19.4s
- sqxtun v16.8b, v16.8h
- sqxtun v17.8b, v17.8h
+ uni_w_post v16, v19, v18, v17, v20, v19
st1 {v16.8b, v17.8b}, [x0], x1
b.hi 1b
ret
@@ -3746,33 +3696,7 @@ function ff_hevc_put_hevc_qpel_uni_w_h24_8_neon, export=1
mla v22.8h, v17.8h, v0.h[5]
mla v22.8h, v18.8h, v0.h[6]
mla v22.8h, v19.8h, v0.h[7]
- smull v16.4s, v20.4h, v30.4h
- smull2 v17.4s, v20.8h, v30.8h
- smull v18.4s, v21.4h, v30.4h
- smull2 v19.4s, v21.8h, v30.8h
- smull v20.4s, v22.4h, v30.4h
- smull2 v21.4s, v22.8h, v30.8h
- sqrshl v16.4s, v16.4s, v31.4s
- sqrshl v17.4s, v17.4s, v31.4s
- sqrshl v18.4s, v18.4s, v31.4s
- sqrshl v19.4s, v19.4s, v31.4s
- sqrshl v20.4s, v20.4s, v31.4s
- sqrshl v21.4s, v21.4s, v31.4s
- sqadd v16.4s, v16.4s, v29.4s
- sqadd v17.4s, v17.4s, v29.4s
- sqadd v18.4s, v18.4s, v29.4s
- sqadd v19.4s, v19.4s, v29.4s
- sqadd v20.4s, v20.4s, v29.4s
- sqadd v21.4s, v21.4s, v29.4s
- sqxtn v16.4h, v16.4s
- sqxtn2 v16.8h, v17.4s
- sqxtn v17.4h, v18.4s
- sqxtn2 v17.8h, v19.4s
- sqxtn v18.4h, v20.4s
- sqxtn2 v18.8h, v21.4s
- sqxtun v16.8b, v16.8h
- sqxtun v17.8b, v17.8h
- sqxtun v18.8b, v18.8h
+ uni_w_post v16, v20, v19, v17, v21, v20, v18, v22, v21
st1 {v16.8b, v17.8b, v18.8b}, [x0], x1
b.hi 1b
ret
@@ -3823,24 +3747,7 @@ function ff_hevc_put_hevc_qpel_uni_w_h32_8_neon, export=1
mla v20.8h, v16.8h, v0.h[5]
mla v20.8h, v17.8h, v0.h[6]
mla v20.8h, v18.8h, v0.h[7]
- smull v16.4s, v19.4h, v30.4h
- smull2 v17.4s, v19.8h, v30.8h
- smull v18.4s, v20.4h, v30.4h
- smull2 v19.4s, v20.8h, v30.8h
- sqrshl v16.4s, v16.4s, v31.4s
- sqrshl v17.4s, v17.4s, v31.4s
- sqrshl v18.4s, v18.4s, v31.4s
- sqrshl v19.4s, v19.4s, v31.4s
- sqadd v16.4s, v16.4s, v29.4s
- sqadd v17.4s, v17.4s, v29.4s
- sqadd v18.4s, v18.4s, v29.4s
- sqadd v19.4s, v19.4s, v29.4s
- sqxtn v16.4h, v16.4s
- sqxtn2 v16.8h, v17.4s
- sqxtn v17.4h, v18.4s
- sqxtn2 v17.8h, v19.4s
- sqxtun v16.8b, v16.8h
- sqxtun v17.8b, v17.8h
+ uni_w_post v16, v19, v18, v17, v20, v19
st1 {v16.8b, v17.8b}, [x0], #16
mov v1.16b, v3.16b
b.gt 1b
--
2.52.0
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