Frank, I design ASICs, and have designed well over 100 of them, so I know
what I say IS true. What you say about scaling the die (pure geometry) IS
correct, and in fact is something I said in one of my posts. But that does
not make a different (smaller or larger) process give a higher yield, they
are two different things.
Typically, the "older" processes, which are larger processes, are what
companies make their high volume, less expensive parts from, simply because
they get a much higher yield from them.
> -----Original Message-----
> From: [EMAIL PROTECTED]
> [mailto:[EMAIL PROTECTED]]On Behalf Of Frank Paris
> Sent: Thursday, February 01, 2001 1:02 AM
> To: [EMAIL PROTECTED]
> Subject: RE: Future of Photography (was filmscanners: real value?)
>
>
> I work for an IC testing company (Credence Systems) and I
> know that what
> you're saying isn't true. In fact, it's just pure geometry.
> You don't even
> have to understand the physics of it.
>
> Frank Paris
> [EMAIL PROTECTED]
> http://albums.photopoint.com/j/AlbumList?u=62684
>
> > It isn't true that because the die is
> > larger simply because of process size, that the yield goes
> > down...in fact it
> > typically goes up.
> >
>
