[This message was posted by Anders Furuhed of Pantor Engineering <[EMAIL PROTECTED]> to the "FAST Protocol" discussion forum at http://fixprotocol.org/discuss/46. You can reply to it on-line at http://fixprotocol.org/discuss/read/da00e10a - PLEASE DO NOT REPLY BY MAIL.]
> You need me to be specific after all those answers below point to the > same conclusion? > > Okay, fine, provide a reference implementation that decodes sad 150,000 > messages on a 3GHz core. Tangible one if possible. > > For the record, that is a pathetic rate by any standards of late > 1990s, and two orders of magnitude improvement is perfectly normal in > this day and age. > > Once again, bits are the wrong abstraction in all hardware architectures > for the last 10 years. Moreover, equivalent bandwidth saving is > achievable with less complexity and latency, try it out yourself (it is > not my job to educate). > > FAST design is going against that, period. > I get the impression that you think a FAST software implementation cannot be be processed at a high rate on contemporary hardware. Is that correct? [You can unsubscribe from this discussion group by sending a message to mailto:[EMAIL PROTECTED] --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "Financial Information eXchange" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [EMAIL PROTECTED] For more options, visit this group at http://groups.google.com/group/FIX-Protocol?hl=en -~----------~----~----~----~------~----~------~--~---
