On Wed, Dec 30, 2009 at 10:28 AM, Michael Karcher <[email protected]> wrote: > Am Montag, den 28.12.2009, 15:21 -0500 schrieb bas nowaira: >> Greetings, >> >> Per my conversation with agaran on irc, please find the attached log of: >> < agaran> !summary bassem >> < flashrom_bot> bassem: please mail the output of 'flashrom -V', >> 'lspci -nnvvvxxx', 'superiotool -deV' (all commands as root), the >> exact >> name of your board (including revision, if there >> are multiple revisions), and a link to the official BIOS download to >> [email protected] >> >> I appreciate all the assistance you can provide. > > The included patch should make flashing on your system possible. As it > is quite big (generic SuperI/O infrastructure for an yet unsupported > chip), it is possible that it doesn't work on the first attempt. > > If it works, please reply to this mail (keeping the Cc: to > [email protected]) containing > "Acked by: bas nowaira <[email protected]>" > (without the quotes) > If it doesn't work, please reply quoting the whole output of flashrom -V > of the patched version. > > Regards, > Michael Karcher > > Signed-Off-By: Michael Karcher <[email protected]> > > Index: board_enable.c > =================================================================== > --- board_enable.c (Revision 824) > +++ board_enable.c (Arbeitskopie) > @@ -205,7 +205,50 @@ > return 0; > } > > +static int pc87360_gpio_set(uint8_t gpio, int raise) > +{ > + static const int bankbase[] = {0, 4, 8, 10, 12}; > + int gpio_bank = gpio / 8; > + int gpio_pin = gpio % 8; > + uint16_t baseport; > + uint8_t id; > + uint8_t val; > > + if (gpio_bank > 4) > + { > + fprintf(stderr, "PC87360: Invalid GPIO %d\n", gpio); > + return -1; > + } > + > + id = sio_read(0x2E, 0x20); > + if (id != 0xE1) > + { > + fprintf(stderr, "PC87360: unexpected ID %02x\n", id); > + return -1; > + } > + > + sio_write(0x2E, 0x07, 0x07); /* select GPIO device */ > + baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); > + if((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) > + { > + fprintf (stderr, "PC87360: invalid GPIO base address %04x\n", > + baseport); > + return -1; > + } > + sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device */ > + sio_write(0x2E, 0xF0, gpio_bank*16 + gpio_pin); > + sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output */ > + > + val = INB(baseport + bankbase[gpio_bank]); > + if(raise) > + val |= 1 << gpio_pin; > + else > + val &= ~(1 << gpio_pin); > + OUTB(val, baseport + bankbase[gpio_bank]); > + > + return 0; > +} > + > /** > * VT823x: Set one of the GPIO pins. > */ > @@ -889,6 +932,21 @@ > } > > /** > + * Suited for HP Vectra VL400: 815 + ICH + PC87360. > + */ > + > +static int board_hp_vl400(const char *name) > +{ > + int ret; > + ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */ > + if (!ret) > + ret = pc87360_gpio_set(0x09, 1); /* #WP ? */ > + if (!ret) > + ret = pc87360_gpio_set(0x27, 1); /* #TBL */ > + return ret; > +} > + > +/** > * Suited for: > * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF > * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705 > @@ -1207,6 +1265,7 @@ > {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, > NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", > it87xx_probe_spi_flash}, > {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, > NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", > it87xx_probe_spi_flash}, > {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, > "hp", "dl145_g3", "HP", "DL145 G3", > board_hp_dl145_g3_enable}, > + {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, > NULL, NULL, "HP", "Vectra VL400", > board_hp_vl400}, > {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, > NULL, NULL, "IBM", "x3455", > board_ibm_x3455}, > {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, > NULL, NULL, "Intel", "D201GLY", > wbsio_check_for_spi}, > {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, > "iwill", "dk8_htx", "IWILL", "DK8-HTX", > w83627hf_gpio24_raise_2e}, > Acked-By: bas nowaira <[email protected]> > >
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