Intel NIC with parallel flash support.
Signed-off-by: Carl-Daniel Hailfinger <[email protected]>
--
http://www.hailfinger.org/
Index: flashrom-nicintel/Makefile
===================================================================
--- flashrom-nicintel/Makefile (Revision 1295)
+++ flashrom-nicintel/Makefile (Arbeitskopie)
@@ -193,6 +193,9 @@
# Always enable Marvell SATA controllers for now.
CONFIG_SATAMV ?= yes
+# Always enable Intel NICs for now.
+CONFIG_NICINTEL ?= yes
+
# Disable wiki printing by default. It is only useful if you have wiki access.
CONFIG_PRINT_WIKI ?= no
@@ -327,6 +330,12 @@
NEED_PCI := yes
endif
+ifeq ($(CONFIG_NICINTEL), yes)
+FEATURE_CFLAGS += -D'CONFIG_NICINTEL=1'
+PROGRAMMER_OBJS += nicintel.o
+NEED_PCI := yes
+endif
+
ifeq ($(NEED_SERIAL), yes)
LIB_OBJS += serial.o
endif
Index: flashrom-nicintel/print_wiki.c
===================================================================
--- flashrom-nicintel/print_wiki.c (Revision 1295)
+++ flashrom-nicintel/print_wiki.c (Arbeitskopie)
@@ -307,6 +307,9 @@
#if CONFIG_SATAMV == 1
print_supported_pcidevs_wiki(satas_mv);
#endif
+#if CONFIG_NICINTEL == 1
+ print_supported_pcidevs_wiki(nics_intel);
+#endif
printf("\n|}\n");
}
Index: flashrom-nicintel/nicintel_spi.c
===================================================================
--- flashrom-nicintel/nicintel_spi.c (Revision 1295)
+++ flashrom-nicintel/nicintel_spi.c (Arbeitskopie)
@@ -63,6 +63,7 @@
const struct pcidev_status nics_intel_spi[] = {
{PCI_VENDOR_ID_INTEL, 0x105e, OK, "Intel", "82571EB Gigabit Ethernet Controller"},
{PCI_VENDOR_ID_INTEL, 0x107c, OK, "Intel", "82541PI Gigabit Ethernet Controller"},
+ {PCI_VENDOR_ID_INTEL, 0x10b6, NT, "Intel", "82598 10GbE PCI-Express Ethernet Controller"},
{PCI_VENDOR_ID_INTEL, 0x10b9, OK, "Intel", "82572EI Gigabit Ethernet Controller"},
{},
Index: flashrom-nicintel/nicintel.c
===================================================================
--- flashrom-nicintel/nicintel.c (Revision 0)
+++ flashrom-nicintel/nicintel.c (Revision 0)
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the flashrom project.
+ *
+ * Copyright (C) 2011 Carl-Daniel Hailfinger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Datasheet: http://download.intel.com/design/network/datashts/82559_Fast_Ethernet_Multifunction_PCI_Cardbus_Controller_Datasheet.pdf */
+
+#include <stdlib.h>
+#include "flash.h"
+#include "programmer.h"
+
+uint8_t *nicintel_bar;
+uint8_t *nicintel_control_bar;
+
+const struct pcidev_status nics_intel[] = {
+ {PCI_VENDOR_ID_INTEL, 0x1209, NT, "Intel", "8255xER/82551IT Fast Ethernet Controller"},
+ {PCI_VENDOR_ID_INTEL, 0x1229, NT, "Intel", "82557/8/9/0/1 Ethernet Pro 100"},
+
+ {},
+};
+
+/* Arbitrary limit, taken from the datasheet I just had lying around.
+ * 128 kByte on the 82559 device. Or not. Depends on whom you ask.
+ */
+#define NICINTEL_MEMMAP_SIZE (128 * 1024)
+#define NICINTEL_MEMMAP_MASK (NICINTEL_MEMMAP_SIZE - 1)
+
+#define CSR_FCR 0x0c
+
+int nicintel_init(void)
+{
+ uintptr_t addr;
+
+ /* Needed only for PCI accesses on some platforms.
+ * FIXME: Refactor that into get_mem_perms/get_io_perms/get_pci_perms?
+ */
+ get_io_perms();
+
+ /* No need to check for errors, pcidev_init() will not return in case
+ * of errors.
+ * FIXME: BAR2 is not available if the device uses the CardBus function.
+ */
+ addr = pcidev_init(PCI_VENDOR_ID_INTEL, PCI_BASE_ADDRESS_2, nics_intel);
+
+ nicintel_bar = physmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE);
+ if (nicintel_bar == ERROR_PTR)
+ goto error_out;
+
+ /* FIXME: Using pcidev_dev _will_ cause pretty explosions in the future. */
+ addr = pcidev_validate(pcidev_dev, PCI_BASE_ADDRESS_0, nics_intel);
+ /* FIXME: This is not an aligned mapping. Use 4k? */
+ nicintel_control_bar = physmap("Intel NIC control/status reg", addr, 0x10);
+ if (nicintel_control_bar == ERROR_PTR)
+ goto error_out;
+
+ /* FIXME: This needs to be an auto-reversible write. */
+ /* FIXME: This register is pretty undocumented in all publicly available
+ * documentation from Intel. Let me quote the complete info we have:
+ * "Flash Control Register: The Flash Control register allows the CPU to
+ * enable writes to an external Flash. The Flash Control Register is a
+ * 32-bit field that allows access to an external Flash device."
+ * Ah yes, we also know where it is, but we have absolutely _no_ idea
+ * what we should do with it. Write 0x0001 because we have nothing
+ * better to do with our time.
+ */
+ pci_mmio_writew(0x0001, nicintel_control_bar + CSR_FCR);
+
+ buses_supported = CHIP_BUSTYPE_PARALLEL;
+
+ max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
+
+ return 0;
+
+error_out:
+ pci_cleanup(pacc);
+ release_io_perms();
+ return 1;
+}
+
+int nicintel_shutdown(void)
+{
+ physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE);
+ pci_cleanup(pacc);
+ release_io_perms();
+ return 0;
+}
+
+void nicintel_chip_writeb(uint8_t val, chipaddr addr)
+{
+ pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
+}
+
+uint8_t nicintel_chip_readb(const chipaddr addr)
+{
+ return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
+}
Index: flashrom-nicintel/flashrom.c
===================================================================
--- flashrom-nicintel/flashrom.c (Revision 1295)
+++ flashrom-nicintel/flashrom.c (Arbeitskopie)
@@ -52,7 +52,7 @@
* if more than one of them is selected. If only one is selected, it is clear
* that the user wants that one to become the default.
*/
-#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV > 1
+#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV+CONFIG_NICINTEL > 1
#error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one.
#endif
enum programmer programmer =
@@ -101,6 +101,9 @@
#if CONFIG_SATAMV == 1
PROGRAMMER_SATAMV
#endif
+#if CONFIG_NICINTEL == 1
+ PROGRAMMER_NICINTEL
+#endif
;
#endif
@@ -447,6 +450,25 @@
},
#endif
+#if CONFIG_NICINTEL == 1
+ {
+ .name = "nicintel",
+ .init = nicintel_init,
+ .shutdown = nicintel_shutdown,
+ .map_flash_region = fallback_map,
+ .unmap_flash_region = fallback_unmap,
+ .chip_readb = nicintel_chip_readb,
+ .chip_readw = fallback_chip_readw,
+ .chip_readl = fallback_chip_readl,
+ .chip_readn = fallback_chip_readn,
+ .chip_writeb = nicintel_chip_writeb,
+ .chip_writew = fallback_chip_writew,
+ .chip_writel = fallback_chip_writel,
+ .chip_writen = fallback_chip_writen,
+ .delay = internal_delay,
+ },
+#endif
+
{}, /* This entry corresponds to PROGRAMMER_INVALID. */
};
Index: flashrom-nicintel/programmer.h
===================================================================
--- flashrom-nicintel/programmer.h (Revision 1295)
+++ flashrom-nicintel/programmer.h (Arbeitskopie)
@@ -76,6 +76,9 @@
#if CONFIG_SATAMV == 1
PROGRAMMER_SATAMV,
#endif
+#if CONFIG_NICINTEL == 1
+ PROGRAMMER_NICINTEL,
+#endif
PROGRAMMER_INVALID /* This must always be the last entry. */
};
@@ -446,6 +449,15 @@
extern const struct pcidev_status satas_mv[];
#endif
+/* nicintel.c */
+#if CONFIG_NICINTEL == 1
+int nicintel_init(void);
+int nicintel_shutdown(void);
+void nicintel_chip_writeb(uint8_t val, chipaddr addr);
+uint8_t nicintel_chip_readb(const chipaddr addr);
+extern const struct pcidev_status nics_intel[];
+#endif
+
/* satasii.c */
#if CONFIG_SATASII == 1
int satasii_init(void);
Index: flashrom-nicintel/print.c
===================================================================
--- flashrom-nicintel/print.c (Revision 1295)
+++ flashrom-nicintel/print.c (Arbeitskopie)
@@ -319,6 +319,11 @@
programmer_table[PROGRAMMER_SATAMV].name);
print_supported_pcidevs(satas_mv);
#endif
+#if CONFIG_NICINTEL == 1
+ printf("\nSupported devices for the %s programmer:\n",
+ programmer_table[PROGRAMMER_NICINTEL].name);
+ print_supported_pcidevs(nics_intel);
+#endif
}
#if CONFIG_INTERNAL == 1
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