Add pinout for ByteBlaster to rayer_spi.c.
Signed-off-by: Maksim Kuleshov <[email protected]>
---
rayer_spi.c | 91 +++++++++++++++++++++++++++++++++++++++--------------------
1 file changed, 61 insertions(+), 30 deletions(-)
diff --git a/rayer_spi.c b/rayer_spi.c
index b312610..488b555 100644
--- a/rayer_spi.c
+++ b/rayer_spi.c
@@ -35,13 +35,28 @@
#include <string.h>
#include "flash.h"
#include "programmer.h"
#include "hwaccess.h"
-enum rayer_type {
- TYPE_RAYER,
- TYPE_XILINX_DLC5,
+
+static void rayer_byteblaster_preinit(void *);
+static int rayer_byteblaster_shutdown(void *);
+
+static struct s_rayer_pinout {
+ const char * name;
+ const char * description;
+ int cs_bit;
+ int sck_bit;
+ int mosi_bit;
+ int miso_bit;
+ void (*preinit)(void *);
+ int (*shutdown)(void *);
+} rayer_pinouts [] = {
+ {"rayer","RayeR SPIPGM",5,6,7,6},
+ {"xilinx","Xilinx Parallel Cable III (DLC 5)",2,1,0,4},
+ {"byteblaster","Altera
ByteBlaster",1,0,6,7,rayer_byteblaster_preinit,rayer_byteblaster_shutdown},
+ {0},
};
/* We have two sets of pins, out and in. The numbers for both sets are
* independent and are bitshift values, not real pin numbers.
* Default settings are for the RayeR hardware.
@@ -81,11 +96,11 @@ static void rayer_bitbang_set_mosi(int val)
static int rayer_bitbang_get_miso(void)
{
uint8_t tmp;
- tmp = INB(lpt_iobase + 1);
+ tmp = INB(lpt_iobase + 1) ^ 0x80;//bit.7 inverted
tmp = (tmp >> rayer_miso_bit) & 0x1;
return tmp;
}
static const struct bitbang_spi_master bitbang_spi_master_rayer = {
@@ -95,14 +110,17 @@ static const struct bitbang_spi_master
bitbang_spi_master_rayer = {
.set_mosi = rayer_bitbang_set_mosi,
.get_miso = rayer_bitbang_get_miso,
.half_period = 0,
};
+
+static void (*rayer_preinit)(void*) =NULL;
+static void * rayer_preinit_data=NULL;
+
int rayer_spi_init(void)
{
char *arg = NULL;
- enum rayer_type rayer_type = TYPE_RAYER;
/* Non-default port requested? */
arg = extract_programmer_param("iobase");
if (arg) {
char *endptr = NULL;
@@ -136,51 +154,64 @@ int rayer_spi_init(void)
msg_pdbg("Using address 0x%x as I/O base for parallel port access.\n",
lpt_iobase);
arg = extract_programmer_param("type");
if (arg) {
- if (!strcasecmp(arg, "rayer")) {
- rayer_type = TYPE_RAYER;
- } else if (!strcasecmp(arg, "xilinx")) {
- rayer_type = TYPE_XILINX_DLC5;
- } else {
+ struct s_rayer_pinout *p = rayer_pinouts;
+ for (; p->name; ++p) {
+ if (! strcasecmp (arg, p->name)) {
+ break;
+ }
+ }
+ if(! p->name) {
msg_perr("Error: Invalid device type specified.\n");
free(arg);
return 1;
}
- }
- free(arg);
- switch (rayer_type) {
- case TYPE_RAYER:
- msg_pdbg("Using RayeR SPIPGM pinout.\n");
- /* Bits for master->slave direction */
- rayer_cs_bit = 5;
- rayer_sck_bit = 6;
- rayer_mosi_bit = 7;
- /* Bits for slave->master direction */
- rayer_miso_bit = 6;
- break;
- case TYPE_XILINX_DLC5:
- msg_pdbg("Using Xilinx Parallel Cable III (DLC 5) pinout.\n");
- /* Bits for master->slave direction */
- rayer_cs_bit = 2;
- rayer_sck_bit = 1;
- rayer_mosi_bit = 0;
- /* Bits for slave->master direction */
- rayer_miso_bit = 4;
+ msg_pinfo("Using %s pinout.\n", p->description);
+ rayer_cs_bit = p->cs_bit;
+ rayer_sck_bit = p->sck_bit;
+ rayer_mosi_bit = p->mosi_bit;
+ rayer_miso_bit = p->miso_bit;
+
+ if(p -> preinit){
+ rayer_preinit = p -> preinit;
+ rayer_preinit_data = p;
+ }
+
+ if(p -> shutdown){
+ register_shutdown(p -> shutdown, (void*)p);
+ }
+
+ free(arg);
}
if (rget_io_perms())
return 1;
/* Get the initial value before writing to any line. */
lpt_outbyte = INB(lpt_iobase);
+ if(rayer_preinit){
+ rayer_preinit(rayer_preinit_data);
+ }
+
if (bitbang_spi_init(&bitbang_spi_master_rayer))
return 1;
return 0;
}
+static void rayer_byteblaster_preinit(void * data){
+ msg_pdbg("byteblaster_init\n");
+ OUTB(2, lpt_iobase + 2 );//clear #EN signal
+}
+
+static int rayer_byteblaster_shutdown(void * data){
+ msg_pdbg("byteblaster_shutdown\n");
+ OUTB(0, lpt_iobase + 2 );//set #EN signal
+ return 0;
+}
+
#else
#error PCI port I/O access is not supported on this architecture yet.
#endif
--
1.7.10.4
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