andor had some problems with how coreboot configured the SPI controller. let's see if this hack fixes that.
Stefan Tauner (2): sbxxx: spibar[0] debug print refinements sbxxx: hack to disable fast reads and force lowest possible SPI clock flash.h | 1 + sb600spi.c | 16 +++++++++++++--- 2 files changed, 14 insertions(+), 3 deletions(-) -- Kind regards, Stefan Tauner _______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
