Add support for AMD's Bolton chipset. The SPI controller on the bolton chipset
uses the same 3-bit speed settings as yangtze, but is otherwise the same as the
hudson chips. Note that the Bolton RRG doesn't specify a speed setting for the
bit setting of 0b111, so I'm assuming that it's the same setting as yangtze.
Signed-off-by: Martin Roth <[email protected]>
Index: sb600spi.c
===================================================================
--- sb600spi.c (revision 1818)
+++ sb600spi.c (working copy)
@@ -51,6 +51,7 @@
CHIPSET_SB7XX, /* SP5100 too */
CHIPSET_SB89XX, /* Hudson-1 too */
CHIPSET_HUDSON234,
+ CHIPSET_BOLTON,
CHIPSET_YANGTZE,
};
static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN;
@@ -137,7 +138,10 @@
if (rev >= 0x11 && rev <= 0x15) {
amd_gen = CHIPSET_HUDSON234;
msg_pdbg("Hudson-2/3/4 detected.\n");
- } else if (rev >= 0x39 && rev <= 0x3A) {
+ } else if (rev == 0x16) {
+ amd_gen = CHIPSET_BOLTON;
+ msg_pdbg("Bolton detected.\n");
+ }else if (rev >= 0x39 && rev <= 0x3A) {
amd_gen = CHIPSET_YANGTZE;
msg_pdbg("Yangtze detected.\n");
} else {
@@ -409,7 +413,7 @@
}
/* See the chipset support matrix for SPI Base_Addr below for an explanation of the symbols used.
- * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 yangtze
+ * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 bolton/yangtze
* 18 rsvd <- fastReadEnable ? <- ? SpiReadMode[0]
* 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1]
*/
@@ -453,6 +457,29 @@
msg_pdbg("FastSpeedNew is %s\n", spispeeds[(tmp >> 8) & 0xf].name);
msg_pdbg("AltSpeedNew is %s\n", spispeeds[(tmp >> 4) & 0xf].name);
msg_pdbg("TpmSpeedNew is %s\n", spispeeds[(tmp >> 0) & 0xf].name);
+ } else if (amd_gen == CHIPSET_BOLTON) {
+
+ static const char *spireadmodes[] = {
+ "Normal (up to 33 MHz)", /* 0 */
+ "Reserved", /* 1 */
+ "Dual IO (1-1-2)", /* 2 */
+ "Quad IO (1-1-4)", /* 3 */
+ "Dual IO (1-2-2)", /* 4 */
+ "Quad IO (1-4-4)", /* 5 */
+ "Normal (up to 66 MHz)", /* 6 */
+ "Fast Read", /* 7 (I'm Assuming... This value isn't in the bolton RRG) */
+ };
+ tmp = mmio_readl(sb600_spibar + 0x00);
+ uint8_t read_mode = ((tmp >> 28) & 0x6) | ((tmp >> 18) & 0x1);
+ msg_pdbg("SpiReadMode=%s (%i)\n", spireadmodes[read_mode], read_mode);
+ if (read_mode != 6) {
+ read_mode = 6; /* Default to "Normal (up to 66 MHz)" */
+ if (set_mode(dev, read_mode) != 0) {
+ msg_perr("Setting read mode to \"%s\" failed.\n", spireadmodes[read_mode]);
+ return 1;
+ }
+ msg_pdbg("Setting read mode to \"%s\" succeeded.\n", spireadmodes[read_mode]);
+ }
} else {
if (amd_gen >= CHIPSET_SB89XX && amd_gen <= CHIPSET_HUDSON234) {
bool fast_read = (mmio_readl(sb600_spibar + 0x00) >> 18) & 0x1;
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