Got it, thanks all for the quick responses. I take it that read-protection of non-described areas (ie where there are gaps in the described regions) is done _implicitly_ by the ICH SPI controller?
In the case of Winbond 25Q64 chips, I saw only write-protection in the datasheet, no chip-level read-protection. +Reardon On Tue, Aug 5, 2014 at 2:41 PM, Stefan Tauner <[email protected]> wrote: > On Tue, 5 Aug 2014 12:55:33 -0400 > TR Reardon <[email protected]> wrote: > >> I tried looking for an answer to this but a quick one didn't surface: when >> flash regions are protected, is this implemented by the flash chip itself >> or by the SPI logic (ie ichspi for Intel programmer)? > > Both, and more. There are 3 common cases: > > 1) was used at least in the last 20 years or so: a GPIO line from the > chipset is connected to the write protection pin (most flash chips have > that). This is usually mainboard-specific and is handled by flashrom in > board_enable.c > > 2) Some flash chips offer software locking mechanisms where some > commands need to be sent to the flash chip to lock and unlock > respective address ranges. Those settings can then also be > hardward-locked via 1) > > 3) are programmer-based protections such those seen on Intel chipsets > where the chipset hardware implements a kind of firewall for the SPI > stream. > > -- > Kind regards/Mit freundlichen Grüßen, Stefan Tauner > _______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
