Hi, Stefan!
Thank you so much for your work!
Unfortunally, i flash this motherboard with latest bios by standart utility
from gigabyte and can't experiment with it now.
There is log file from reading flash in attachment.
Воскресенье, 8 февраля 2015, 23:08 +01:00 от Stefan Tauner
<[email protected]>:
>On Fri, 09 Jan 2015 10:34:38 +0300
>Александр Трубицын < [email protected] > wrote:
>
>>
>> Hello!
>> I have Gigabyte H55M-S2H motherboard with 2 MX25L6465EM2I SPI flash chips,
>> but now flashrom asks me to choose from 3 different chips:
>> Multiple flash chip definitions match the detected chip(s): "MX25L6405(D)",
>> "MX25L6406E/MX25L6436E", "MX25L6445E/MX25L6473E"
>> Please specify which chip definition to use with the -c <chipname> option.
>>
>> I find chip datasheet where:
>> http://www.datasheetarchive.com/dl/Datasheets-IS78/DSAH00369299.pdf
>> In the table 6 (ID Definitions) of this datasheet we can see RDID=0x2017
>> 1. Is it possible to use one of supposed chip or a new one?
>> 2. Can you add comment about MX25L6465 in the flashchips.h after MX25L6405
>> or new definition in flashchips.c ?
>> 3. Is it possible to determine flash chip by RDID and RES (Read Electronic
>> Signature)?
>>
>
>Hi,
>
>I have added MX25L6465 in r1879. It is now part of
>"MX25L6445E/MX25L6465E/MX25L6473E". In your version you can simply use
>-c "MX25L6445E/MX25L6473E" and it should work correctly.
>--
>Kind regards/Mit freundlichen Grüßen, Stefan Tauner
flashrom v0.9.8-r1888 on Linux 3.19.3-1-desktop (x86_64)
flashrom was built with libpci 3.3.0, GCC 4.8.3 20141208 [gcc-4_8-branch
revision 218481], little endian
Command line (8 args): /usr/sbin/flashrom -p internal -c
MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E -Vr H55M-S2H_20150421203213.flash
-o H55M-S2H_20150421203213.flash_read.txt
Calibrating delay loop... OS timer resolution is 1 usecs, 1509M loops per
second, 10 myus = 10 us, 100 myus = 98 us, 1000 myus = 988 us, 10000 myus =
9860 us, 4 myus = 4 us, OK.
Initializing internal programmer
No coreboot table found.
Using Internal DMI decoder.
DMI string chassis-type: "Desktop"
DMI string system-manufacturer: "Gigabyte Technology Co., Ltd."
DMI string system-product-name: "H55M-S2H"
DMI string system-version: " "
DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd."
DMI string baseboard-product-name: "H55M-S2H"
DMI string baseboard-version: "x.x"
Found ITE Super I/O, ID 0x8720 on port 0x2e
Found chipset "Intel H55" with PCI ID 8086:3b06.
Enabling flash write... Root Complex Register Block address = 0xfed1c000
GCS = 0xc64: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 (SPI)
Top Swap: not enabled
0xfff80000/0xffb80000 FWH IDSEL: 0x0
0xfff00000/0xffb00000 FWH IDSEL: 0x0
0xffe80000/0xffa80000 FWH IDSEL: 0x1
0xffe00000/0xffa00000 FWH IDSEL: 0x1
0xffd80000/0xff980000 FWH IDSEL: 0x2
0xffd00000/0xff900000 FWH IDSEL: 0x2
0xffc80000/0xff880000 FWH IDSEL: 0x3
0xffc00000/0xff800000 FWH IDSEL: 0x3
0xff700000/0xff300000 FWH IDSEL: 0x4
0xff600000/0xff200000 FWH IDSEL: 0x5
0xff500000/0xff100000 FWH IDSEL: 0x6
0xff400000/0xff000000 FWH IDSEL: 0x7
0xfff80000/0xffb80000 FWH decode enabled
0xfff00000/0xffb00000 FWH decode enabled
0xffe80000/0xffa80000 FWH decode enabled
0xffe00000/0xffa00000 FWH decode enabled
0xffd80000/0xff980000 FWH decode enabled
0xffd00000/0xff900000 FWH decode enabled
0xffc80000/0xff880000 FWH decode enabled
0xffc00000/0xff800000 FWH decode enabled
0xff700000/0xff300000 FWH decode disabled
0xff600000/0xff200000 FWH decode disabled
0xff500000/0xff100000 FWH decode disabled
0xff400000/0xff000000 FWH decode disabled
Maximum FWH chip size: 0x100000 bytes
SPI Read Configuration: prefetching disabled, caching enabled,
BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled
SPIBAR = 0x00007f1b89c3a000 + 0x3800
0x04: 0x6008 (HSFS)
HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0
Programming OPCODES...
program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190
done
OP Type Pre-OP
op[0]: 0x02, write w/ addr, none
op[1]: 0x03, read w/ addr, none
op[2]: 0xd8, write w/ addr, none
op[3]: 0x05, read w/o addr, none
op[4]: 0x90, read w/ addr, none
op[5]: 0x01, write w/o addr, none
op[6]: 0x9f, read w/o addr, none
op[7]: 0xc7, write w/o addr, none
Pre-OP 0: 0x06, Pre-OP 1: 0x50
0x06: 0x0000 (HSFC)
HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0
0x08: 0x00000000 (FADDR)
0x50: 0x0000ffff (FRAP)
BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff
0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is
read-write.
0x58: 0x07ff0000 FREG1: BIOS region (0x00000000-0x007fffff) is read-write.
0x5C: 0x04f20001 FREG2: Management Engine region (0x00001000-0x004f2fff) is
read-write.
0x60: 0x00000fff FREG3: Gigabit Ethernet region is unused.
0x64: 0x00000fff FREG4: Platform Data region is unused.
0x74: 0x00000000 (PR0 is unused)
0x78: 0x00000000 (PR1 is unused)
0x7C: 0x00000000 (PR2 is unused)
0x80: 0x00000000 (PR3 is unused)
0x84: 0x00000000 (PR4 is unused)
0x90: 0x04 (SSFS)
SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0
0x91: 0xf84140 (SSFC)
SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=1, SME=0, SCF=0
0x94: 0x5006 (PREOP)
0x96: 0x463b (OPTYPE)
0x98: 0x05d80302 (OPMENU)
0x9C: 0xc79f0190 (OPMENU+4)
0xA0: 0x00000000 (BBAR)
0xC4: 0x00002005 (LVSCC)
LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0
0xC8: 0x00002005 (UVSCC)
UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20
0xD0: 0x00000000 (FPB)
Reading flash descriptors mapped by the chipset via FDOC/FDOD... done.
=== Content Section ===
FLVALSIG 0x0ff0a55a
FLMAP0 0x02040002
FLMAP1 0x10100206
FLMAP2 0x00000020
--- Details ---
NR (Number of Regions): 3
FRBA (Flash Region Base Address): 0x040
NC (Number of Components): 1
FCBA (Flash Component Base Address): 0x020
ISL (ICH/PCH Strap Length): 16
FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100
NM (Number of Masters): 3
FMBA (Flash Master Base Address): 0x060
MSL/PSL (MCH/PROC Strap Length): 0
FMSBA (Flash MCH/PROC Strap Base Address): 0x200
=== Component Section ===
FLCOMP 0x0930001c
FLILL 0x00000000
--- Details ---
Component 1 density: 8 MB
Component 2 is not used.
Read Clock Frequency: 20 MHz
Read ID and Status Clock Freq.: 33 MHz
Write and Erase Clock Freq.: 33 MHz
Fast Read is supported.
Fast Read Clock Frequency: 33 MHz
No forbidden opcodes.
=== Region Section ===
FLREG0 0x00000000
FLREG1 0x07ff0000
FLREG2 0x04f20001
FLREG3 0x00000fff
FLREG4 0x00000fff
--- Details ---
Region 0 (Descr.) 0x00000000 - 0x00000fff
Region 1 (BIOS ) 0x00000000 - 0x007fffff
Region 2 (ME ) 0x00001000 - 0x004f2fff
Region 3 (GbE ) is unused.
Region 4 (Platf.) is unused.
=== Master Section ===
FLMSTR1 0xffff0000
FLMSTR2 0xffff0000
FLMSTR3 0xffff0118
--- Details ---
Descr. BIOS ME GbE Platf.
BIOS rw rw rw rw rw
ME rw rw rw rw rw
GbE rw rw rw rw rw
OK.
No IT87* serial flash segment enabled.
The following protocols are supported: FWH, SPI.
Probing for Macronix MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E, 8192 kB:
probe_spi_rdid_generic: id1 0xc2, id2 0x2017
Found Macronix flash chip "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E" (8192
kB, SPI) mapped at physical address 0x00000000ff800000.
Chip status register is 0x00.
Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set
Chip status register: Bit 6 is not set
Chip status register: Block Protect 3 (BP3) is not set
Chip status register: Block Protect 2 (BP2) is not set
Chip status register: Block Protect 1 (BP1) is not set
Chip status register: Block Protect 0 (BP0) is not set
Chip status register: Write Enable Latch (WEL) is not set
Chip status register: Write In Progress (WIP/BUSY) is not set
This chip may contain one-time programmable memory. flashrom cannot read
and may never be able to write it, hence it may not be able to completely
clone the contents of this chip (see man page for details).
Block protection is disabled.
Reading flash... done.
Restoring MMIO space at 0x7f1b89c3d8a0
Restoring MMIO space at 0x7f1b89c3d89c
Restoring MMIO space at 0x7f1b89c3d898
Restoring MMIO space at 0x7f1b89c3d896
Restoring MMIO space at 0x7f1b89c3d894
Restoring PCI config space for 00:1f:0 reg 0xdc
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