On Wednesday 25 May 2016 02:26 AM, David Hendricks wrote:
As Stefan points out, some decisions were made in ChromiumOS to avoid
modifying generic code and (in theory) make upstreaming easier. The
writeprotect stuff is the main example. We can re-visit some of those
decisions and put some code in generic locations if it makes sense to do so.
Thanks for the explanation. Highlighting use cases was helpful in
understanding. I shall try to formulate future models based on clear use
cases to convey more effectively.
I don't like the idea of using a FEATURE_SR2 bit - It doesn't describe
the functionality it represents in a useful manner IMO. As you point
out, reading SR2 needlessly can slow things down, especially for the
common use case where we only really care about reading the busy bit.
Agreed. This was what I had in mind when I mentioned it.
For the write protection use case, the exact layout of the status
registers needs to be taken into account, not just whether SR2 is
present or not since SR2 is not as well standardized. To make matters
more complicated, Gigadevice GD25Q128 even has a 3rd status register
which has a bit that defines the entire write-protection scheme. Also,
some chips such as Spansion S25FS and S25FL series don't use status
registers in the same manner as other chips and instead define a set of
control registers with special opcodes to read/write them.
Also, as Stefan points out, the status register bits are relevant to 4B
addressing and quad I/O in addition to write protection. The
implementation details are non-uniform.
I looked at the datasheets of the 28 SPI chips supported in flashrom
that have multiple status registers. 24 of them have 35h opcode for
RDSR2. Atmel(1) and Spansion(2) are complicated. And so is GD25Q128C.
Consequently, I think we need a combination of #2 and #3. For #2, we'll
have functions which read the status registers (but must be careful
since reading SR2 and SR3 aren't standardized AFAIK). For #3 we can
describe the functionality we desire in a reasonably generic way and add
chip-specific helper functions to carry out the task regardless of where
the bits we are interested in reside. I started going in this direction
for ChromiumOS's writeprotect.c, but it's still a work in progress:
https://chromium-review.googlesource.com/#/c/208271/
https://chromium-review.googlesource.com/#/c/259440/
https://chromium-review.googlesource.com/#/c/335822/
https://chromium-review.googlesource.com/#/c/335823/
So, based on the Chromium OS implementation (along with these patches, 2
of which I had to merge locally), this is the revised model. I agree
that a combination of #2 and #3 will offer flexibility and can
definitely convey more information.
- enum status_register_bits enumerates all possible bits that we have
- array of struct status_register_layout as part of struct flashchip
- each array represents a status register and each element of array
represents the bit (using the enum)
- (*read_status)() within struct flashchip taking as argument which
status register to read (SR1 or SR2 or SR3)
- (*write_status)() within struct flashchip
In addition to the above basic elements, we can have
- const char *status_register_bit_name[] that has string-ified
representation of corresponding bit from enum
- array of int status_bit indexed by enum status_register_bits which is
populated when corresponding read_status() is called
To better convey the model, I have implemented some prototype code.
Please have a look at the attached file. And have a look here
(http://paste.flashrom.org/view.php?id=2918) for the output. Please
ignore the violation of 112-character limit in the attached file.
Please let me know your feedback on the model and on the
proof-of-concept implementation. I would also love to hear
suggestions/advice on the code style and quality.
tl;dr version: Overall I think we should just do the work of
representing the status register bits in a generic way, as you describe
in #3. It will be tedious at first, but many chips will be able to share
the same accessor functions. It's very important to be flexible so that
we don't end up with "square peg in a round hole" over-generalizing and
relying too heavily on if-statements/switch statements (a mistake I made
in the chromiumos sources).
I think a solution to making it less tedious would be to write a script
to do as much of the modification as possible, and then manually deal
with outliers. Based on comments in flashchips.c, we have 28 chips with
more than one status register out of a total of 293 SPI chips (revisions
that share definition are not considered different).
Intuitively I think it best to roll out this feature in phases such that
until the final phase, current (vanilla) flashrom behaviour exists in
parallel.
On Tue, May 24, 2016 at 2:07 AM, Stefan Tauner
<[email protected]
<mailto:[email protected]>> wrote:
On Tue, 24 May 2016 12:49:51 +0530
Hatim Kanchwala <[email protected] <mailto:[email protected]>> wrote:
> Hi,
>
> The GSoC coding period has started and I have been working on my
first
> sub-project, adding support for 2nd status register. Most supported
> chips that have multiple registers (around 80%) have opcode 0x35 for
> reading SR2 and, opcode 0x01 for writing SR2. I have developed 3
models
> and would like to have some feedback on them.
>
> 1. Integrate read/write SR2 with existing functions
> PROPOSAL -
> - Define a feature bit FEATURE_SR2
> - spi_read_status_register(), defined in spi25_statusreg.c,
additionally
> reads second status register depending on FEATURE_SR2 bit for
that flash
> - Change return to uint16_t for spi_read_status_register()
> - spi_write_status_register_flag(), defined in spi25_statusreg.c,
> considers higher byte of status to write to SR2, depending on
> FEATURE_SR2 bit for that flash.
> MERITS -
> - Fits in elegantly with existing implementation (IMO). Most code in
> flashrom stores status reads/writes in int, which can easily
accommodate
> the 16 bits
> - Very little hassle when editing struct flashchip in flashchips.c
>
> DEMERITS -
> - RDSR will take more time - will read SR2 even if not needed
>
> 2. Define separate functions to read/write SR2
> PROPOSAL -
> - Define spi_read_status_register2() to read only SR2
> - Define spi_write_status_register2_flag() and
> spi_write_status_register2() to write to SR2. This will read SR1
first,
> then (SR2 << 8 | SR1) will be written using WRSR
>
> MERITS -
> - Flexibility (as compared to 1.)
>
> DEMERITS -
> - Need to write more lines (compared to 1.) when dealing with struct
> flashchip
>
> 3. struct status_register_layout
> The ChromiumOS fork defines a struct status_register_layout in
> writeprotect.c, which contains only BP and SRP bits' information.
> PROPOSAL -
> Do a similar flashrom-wide definition, which contains all status
> register bits' information.
>
> MERITS -
> - Very detailed representation of information
>
> DEMERITS -
> - Too much work when adding support for new chips
> - Overhaul of existing infrastructure
>
> IMHO, the first model is the best among these 3. I would like to know
> what you guys think about these, whether you have some new idea.
Looking
> forward to your feedback. Thanks for your time.
Hi,
thanks Hatim for this summary. It may make sense if David could sum up
the rationales behind the chromiumos implementation. AFAIK much of that
is driven by the desire to not touch flashchips.c to ease later
upstreaming. A more detailed explanation might help Hatim.
What I miss from Hatim's proposals is how use cases affect the various
implementations. The main question that needs to be addressed before
implementing any kind of infrastructure like this is: what do we want
to do with it once it is there.
Till now (vanilla) flashrom did only access the status registers for
gathering (and printing) the status, especially the write protection
bits, and for unlocking said bits.
In the future we want to at least be able to set various protections
additionally. What else do we need? Some bits are relevant to 4B
addressing and Quad I/O too for example...
--
Kind regards/Mit freundlichen Grüßen, Stefan Tauner
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--
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
Thanks for your time.
Bye,
Hatim
#include <stdio.h>
#include <stdint.h>
#define MAX_STATUS_REGISTER_BITS 25
enum status_register_bits {
// Start from 1 (reason apparent in num_status_register() definition body).
WIP = 1, WEL, BP4, BP3, BP2, BP1, BP0, LB3, LB2, LB1, CMP,
WPS, SRP0, SRP1, RESV, QE, SUS1, SUS2, DRV0, DRV1, RST
};
const char *status_register_bit_name[] = {
[WIP] = "WIP", [WEL] = "WEL", [BP4] = "BP4", [BP3] = "BP3",
[BP2] = "BP2", [BP1] = "BP1", [BP0] = "BP0", [LB3] = "LB3",
[LB2] = "LB2", [LB1] = "LB1", [CMP] = "CMP", [WPS] = "WPS",
[SRP0] = "SRP0", [SRP1] = "SRP1", [RESV] = "RESV", [QE] = "QE",
[SUS1] = "SUS1", [SUS2] = "SUS2", [DRV0] = "DRV0",
[DRV1] = "DRV1", [RST] = "RST"
};
// SPI chip with more than 3 status registers not spotted till now, so 3 is max.
enum status_register_num { SR1, SR2, SR3 };
struct status_register_layout {
// Each status register has exactly 8 bits
enum status_register_bits bits[8];
};
struct flashchip {
struct status_register_layout status_register[3];
int status_bit[MAX_STATUS_REGISTER_BITS];
uint8_t (*read_status)(struct flashchip *flash, enum status_register_num);
int (*write_status)(struct flashchip *flash, int status);
};
int num_status_register(struct flashchip *flash) {
int num = 0;
struct status_register_layout *status = flash->status_register;
while (status[num++].bits[0] != 0)
;
return --num;
}
void print_status_register(struct flashchip *flash, enum status_register_num sr) {
printf("SR%d : ", sr + 1);
for (int j = 0; j < 8; j++)
printf("%s ", status_register_bit_name[flash->status_register[sr].bits[j]]);
printf("\n");
}
int bp_bitfield(struct flashchip *flash) {
int mask = 0, i = 0;
while (flash->status_register[SR1].bits[i] != BP0)
i++;
mask = 1 << i;
i++;
while (flash->status_register[SR1].bits[i] == BP4 | flash->status_register[SR1].bits[i] == BP3 | flash->status_register[SR1].bits[i] == BP2 | flash->status_register[SR1].bits[i] == BP1)
mask = mask | (1 << (i++));
return mask;
}
uint8_t read_status_dummy(struct flashchip *flash, enum status_register_num sr) {
// This will come from the chip
int status = 0xA8;
for (int i = 0; i < 8; i++)
flash->status_bit[flash->status_register[sr].bits[i]] = (status & (1 << i)) >> i;
return (uint8_t)status;
}
int main(int argc, const char **argv) {
struct flashchip flash = {
.status_register = {
[SR1] = { WIP, WEL, BP0, BP1, BP2, BP3, BP4, SRP0 },
[SR2] = { SRP1, QE, SUS2, LB1, LB2, LB3, CMP, SUS1 },
[SR3] = { RESV, RESV, WPS, RESV, RESV, DRV0, DRV1, RST },
},
.read_status = read_status_dummy,
};
printf("num_status_register = %d\n", num_status_register(&flash));
print_status_register(&flash, SR1);
print_status_register(&flash, SR2);
print_status_register(&flash, SR3);
printf("BP mask = 0x%02x\n", bp_bitfield(&flash));
flash.read_status(&flash, SR1);
flash.read_status(&flash, SR2);
flash.read_status(&flash, SR3);
printf("%s=%d, %s=%d\n", status_register_bit_name[BP0], flash.status_bit[BP0], status_register_bit_name[LB1], flash.status_bit[LB1]);
return 0;
}
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