Hi,
I try to write bios. However, I always got “No EEPROM/flash device found”.
Could you give me some suggestions.
Thanks
Jason.Huang
黃宏宗
Delta Networks, INC.
TEL：+886-2-8797-3250 ext.3050
E-Mail：[email protected]
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root@genericx86-64:~# flashrom -p internal -f -w 1.bin -c
"MX25L12835F/MX25L12845E/MX25L12865E" -VV
flashrom v0.9.9-90-g22f2dc5 on Linux 4.12.12-yocto-standard (x86_64)
flashrom is free software, get the source code at https://flashrom.org
flashrom was built with libpci 3.5.5, GCC 7.2.0, little endian
Command line (8 args): flashrom -p internal -f -w 1.bin -c
MX25L12835F/MX25L12845E/MX25L12865E -VV
Calibrating delay loop... OS timer resolution is 1 usecs, Initializing internal
programmer
No coreboot table found.
Using Internal DMI decoder.
DMI string chassis-type: "Rack Mount Chassis"
DMI string system-manufacturer: "Default string"
DMI string system-product-name: "Default string"
DMI string system-version: "Default string"
DMI string baseboard-manufacturer: "Default string"
DMI string baseboard-product-name: "Default string"
DMI string baseboard-version: "Default string"
Found chipset "Intel C224" with PCI ID 8086:8c54.
This chipset is marked as untested. If you are using an up-to-date version
of flashrom *and* were (not) able to successfully update your firmware with it,
then please email a report to [email protected] including a verbose (-V)
log.
Thank you!
Enabling flash write... Root Complex Register Block address = 0xfed1c000
GCS = 0xc21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI)
Top Swap: not enabled
0xfff80000/0xffb80000 FWH IDSEL: 0x0
0xfff00000/0xffb00000 FWH IDSEL: 0x0
0xffe80000/0xffa80000 FWH IDSEL: 0x1
0xffe00000/0xffa00000 FWH IDSEL: 0x1
0xffd80000/0xff980000 FWH IDSEL: 0x2
0xffd00000/0xff900000 FWH IDSEL: 0x2
0xffc80000/0xff880000 FWH IDSEL: 0x3
0xffc00000/0xff800000 FWH IDSEL: 0x3
0xff700000/0xff300000 FWH IDSEL: 0x4
0xff600000/0xff200000 FWH IDSEL: 0x5
0xff500000/0xff100000 FWH IDSEL: 0x6
0xff400000/0xff000000 FWH IDSEL: 0x7
0xfff80000/0xffb80000 FWH decode enabled
0xfff00000/0xffb00000 FWH decode enabled
0xffe80000/0xffa80000 FWH decode enabled
0xffe00000/0xffa00000 FWH decode enabled
0xffd80000/0xff980000 FWH decode enabled
0xffd00000/0xff900000 FWH decode enabled
0xffc80000/0xff880000 FWH decode enabled
0xffc00000/0xff800000 FWH decode enabled
0xff700000/0xff300000 FWH decode enabled
0xff600000/0xff200000 FWH decode enabled
0xff500000/0xff100000 FWH decode enabled
0xff400000/0xff000000 FWH decode enabled
Maximum FWH chip size: 0x100000 bytes
SPI Read Configuration: prefetching enabled, caching enabled,
BIOS_CNTL = 0x2b: BIOS Lock Enable: enabled, BIOS Write Enable: enabled
Warning: BIOS region SMM protection is enabled!
Warning: Setting Bios Control at 0xdc from 0x2b to 0x09 failed.
New value is 0x2b.
SPIBAR = 0x00007f3542a1b000 + 0x3800
0x04: 0xf008 (HSFS)
HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1
Warning: SPI Configuration Lockdown activated.
Reading OPCODES... done
OP Type Pre-OP
op[0]: 0x02, write w/ addr, none
op[1]: 0x03, read w/ addr, none
op[2]: 0x20, write w/ addr, none
op[3]: 0x05, read w/o addr, none
op[4]: 0x9f, read w/o addr, none
op[5]: 0x01, write w/o addr, none
op[6]: 0x00, read w/o addr, none
op[7]: 0x5a, read w/ addr, none
Pre-OP 0: 0x06, Pre-OP 1: 0x00
0x06: 0x0300 (HSFC)
HSFC: FGO=0, FCYCLE=0, FDBC=3, SME=0
0x08: 0x01855730 (FADDR)
0x50: 0x00007b7b (FRAP)
BMWAG 0x00, BMRAG 0x00, BRWA 0x7b, BRRA 0x7b
0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is
read-write.
0x58: 0x1fff1800 FREG1: BIOS region (0x01800000-0x01ffffff) is read-write.
0x5C: 0x17ff0023 FREG2: Warning: Management Engine region
(0x00023000-0x017fffff) is locked.
0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is
read-write.
0x64: 0x00120003 FREG4: Platform Data region (0x00003000-0x00012fff) is
read-write.
Not all flash regions are freely accessible by flashrom. This is most likely
due to an active ME. Please see https://flashrom.org/ME for details.
0x74: 0x00000000 (PR0 is unused)
0x78: 0x00000000 (PR1 is unused)
0x7C: 0x00000000 (PR2 is unused)
0x80: 0x00000000 (PR3 is unused)
0x84: 0x00000000 (PR4 is unused)
Writes have been disabled for safety reasons. You can enforce write
support with the ich_spi_force programmer option, but you will most likely
harm your hardware! If you force flashrom you will get no support if
something breaks. On a few mainboards it is possible to enable write
access by setting a jumper (see its documentation or the board itself).
0x90: 0x80 (SSFS)
SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0
0x91: 0xf84030 (SSFC)
SSFC: SCGO=0, ACS=0, SPOP=0, COP=3, DBC=0, SME=0, SCF=0
0x94: 0x0006 (PREOP)
0x96: 0x843b (OPTYPE)
0x98: 0x05200302 (OPMENU)
0x9c: 0x5a00019f (OPMENU+4)
0xA0: 0x00000000 (BBAR)
0xC4: 0x8080d817 (LVSCC)
LVSCC: BES=0x3, WG=1, WSR=0, WEWS=1, EO=0xd8, VCL=1
0xC8: 0x8000d817 (UVSCC)
UVSCC: BES=0x3, WG=1, WSR=0, WEWS=1, EO=0xd8
0xD0: 0x50444653 (FPB)
Reading flash descriptors mapped by the chipset via FDOC/FDOD... done.
=== Content Section ===
FLVALSIG 0x0ff0a55a
FLMAP0 0x05040103
FLMAP1 0x15100306
FLMAP2 0x26210120
--- Details ---
NR (Number of Regions): 6
FRBA (Flash Region Base Address): 0x040
NC (Number of Components): 2
FCBA (Flash Component Base Address): 0x030
ISL (ICH/PCH Strap Length): 21
FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100
NM (Number of Masters): 4
FMBA (Flash Master Base Address): 0x060
MSL/PSL (MCH/PROC Strap Length): 1
FMSBA (Flash MCH/PROC Strap Base Address): 0x200
=== Component Section ===
FLCOMP 0x24900055
FLILL 0x00000000
--- Details ---
Component 1 density: 16 MB
Component 2 density: 16 MB
Read Clock Frequency: 20 MHz
Read ID and Status Clock Freq.: 50 MHz
Write and Erase Clock Freq.: 50 MHz
Fast Read is supported.
Fast Read Clock Frequency: 50 MHz
Dual Output Fast Read Support: enabled
No forbidden opcodes.
=== Region Section ===
FLREG0 0x00000000
FLREG1 0x1fff1800
FLREG2 0x17ff0023
FLREG3 0x00020001
FLREG4 0x00120003
FLREG5 0x00000000
--- Details ---
Region 0 (Descr. ) 0x00000000 - 0x00000fff
Region 1 (BIOS ) 0x01800000 - 0x01ffffff
Region 2 (ME ) 0x00023000 - 0x017fffff
Region 3 (GbE ) 0x00001000 - 0x00002fff
Region 4 (Platf. ) 0x00003000 - 0x00012fff
Region 5 (unknown) 0x00000000 - 0x00000fff
=== Master Section ===
FLMSTR1 0x3b3b0000
FLMSTR2 0x04250000
FLMSTR3 0x08090118
FLMSTR4 0x00000000
--- Details ---
Descr. BIOS ME GbE Platf.
BIOS rw rw rw rw
ME r rw
GbE r rw
Enabling hardware sequencing due to multiple flash chips detected.
OK.
The following protocols are supported: FWH, Programmer-specific.
No EEPROM/flash device found.
Restoring MMIO space at 0x7f3542a1e8a0
Restoring PCI config space for 00:1f:0 reg 0xdc
root@genericx86-64:~# lspci
00:00.0 Host bridge: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D
DMI2 (rev 03)
00:01.0 PCI bridge: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D
PCI Express Root Port 1 (rev 03)
00:01.1 PCI bridge: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D
PCI Express Root Port 1 (rev 03)
00:02.0 PCI bridge: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D
PCI Express Root Port 2 (rev 03)
00:02.2 PCI bridge: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D
PCI Express Root Port 2 (rev 03)
00:03.0 PCI bridge: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D
PCI Express Root Port 3 (rev 03)
00:03.1 PCI bridge: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D
PCI Express Root Port 3 (rev 03)
00:03.2 PCI bridge: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D
PCI Express Root Port 3 (rev 03)
00:05.0 System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3
v4/Xeon D Map/VTd_Misc/System Management (rev 03)
00:05.1 System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3
v4/Xeon D IIO Hot Plug (rev 03)
00:05.2 System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3
v4/Xeon D IIO RAS/Control Status/Global Errors (rev 03)
00:05.4 PIC: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D I/O APIC
(rev 03)
00:14.0 USB controller: Intel Corporation 8 Series/C220 Series Chipset Family
USB xHCI (rev 05)
00:16.0 Communication controller: Intel Corporation 8 Series/C220 Series
Chipset Family MEI Controller #1 (rev 04)
00:16.1 Communication controller: Intel Corporation 8 Series/C220 Series
Chipset Family MEI Controller #2 (rev 04)
00:1c.0 PCI bridge: Intel Corporation 8 Series/C220 Series Chipset Family PCI
Express Root Port #1 (rev d5)
00:1c.1 PCI bridge: Intel Corporation 8 Series/C220 Series Chipset Family PCI
Express Root Port #2 (rev d5)
00:1d.0 USB controller: Intel Corporation 8 Series/C220 Series Chipset Family
USB EHCI #1 (rev 05)
00:1f.0 ISA bridge: Intel Corporation C224 Series Chipset Family Server
Standard SKU LPC Controller (rev 05)
00:1f.2 SATA controller: Intel Corporation 8 Series/C220 Series Chipset Family
6-port SATA Controller 1 [AHCI mode] (rev 05)
00:1f.3 SMBus: Intel Corporation 8 Series/C220 Series Chipset Family SMBus
Controller (rev 05)
02:00.0 Ethernet controller: Broadcom Limited Device 9800
03:00.0 System peripheral: Intel Corporation Xeon Processor D Family QuickData
Technology Register DMA Channel 0
03:00.1 System peripheral: Intel Corporation Xeon Processor D Family QuickData
Technology Register DMA Channel 1
03:00.2 System peripheral: Intel Corporation Xeon Processor D Family QuickData
Technology Register DMA Channel 2
03:00.3 System peripheral: Intel Corporation Xeon Processor D Family QuickData
Technology Register DMA Channel 3
04:00.0 Ethernet controller: Intel Corporation Ethernet Connection X552 10 GbE
Backplane
04:00.1 Ethernet controller: Intel Corporation Ethernet Connection X552 10 GbE
Backplane
06:00.0 Ethernet controller: Broadcom Limited Device 8380 (rev 02)
06:00.1 Ethernet controller: Broadcom Limited Device 8380 (rev 02)
0a:00.0 Ethernet controller: Intel Corporation Device 1531 (rev 03)
root@genericx86-64:~#_______________________________________________
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