Hi Rafael, > So would the solution be to flash the larger chip with some external tool > like a Raspberry Pi and adjust the size of the CBFS in coreboot (can do both, > shouldn't be a problem).
That's part of it. However, you still need to update the flash descriptor contents (bottom 4KiB of the ROM image) so that it describes the larger flash chip you wish to use. Details about the flash descriptor layout can be found in "SPI Programming Guide" documents from Intel which may require registering an account on developer.intel.com and agreeing to their terms. > I guess I'll need some other payload with a SPI driver to access the > remaining space (u-boot? No luck there so far..) right? The limitation that Nico describes is due to the way the SPI controller works on modern Intel platforms. Software/firmware running on the CPU will not be able to access any ROM region that is not defined with appropriate parameters in the flash descriptor. _______________________________________________ flashrom mailing list -- [email protected] To unsubscribe send an email to [email protected]
