This is good news, I can see your patch! You pushed your patch successfully, which you can see from the logs you posted earlier, and also the logs contain the link to the patch (https://review.coreboot.org/c/flashrom/+/81970 in this case). You can click the link and inspect how your patch looks, how Gerrit UI looks. View-only mode is public (you can send the link to anyone), but to modify your patch, respond to comments etc, you need to be logged into Gerrit.
Next steps are documented in the section "Going through code reviews" here https://flashrom.org/dev_guide/development_guide.html#going-through-code-reviews During the code review process communication is happening in Gerrit (not in the mailing list). So your immediate next step is to wait for reviewer(s) to go through your patch and add comments, it will happen soon. And then you need to fix and respond to comments. There are more details in the doc I linked. Thank you for your work! And keep an eye on your patch when the comments arrive. On Fri, Apr 19, 2024 at 6:03 AM Vlim <v...@gigadevice.com> wrote: > > Thanks, > > I think I am getting closer. What do I do next? > > Regards, > > Victor > > > victor@victor-0-1:~/Desktop/flashrom$ git push upstream HEAD:refs/for/main > Username for 'https://review.coreboot.org': victorswlim > Password for 'https://victorsw...@review.coreboot.org': > Enumerating objects: 9, done. > Counting objects: 100% (9/9), done. > Delta compression using up to 8 threads > Compressing objects: 100% (5/5), done. > Writing objects: 100% (5/5), 1.74 KiB | 445.00 KiB/s, done. > Total 5 (delta 4), reused 0 (delta 0), pack-reused 0 > remote: Resolving deltas: 100% (4/4) > remote: Processing changes: refs: 1, new: 1, done > remote: > remote: SUCCESS > remote: > remote: https://review.coreboot.org/c/flashrom/+/81970 <Flashrom SPI NOR>: > adding a few new SPI NOR part numbers [NEW] > remote: > To https://review.coreboot.org/flashrom > * [new reference] HEAD -> refs/for/main > > > ________________________________ > From: Anastasia Klimchuk <a...@chromium.org> > Sent: Thursday, April 18, 2024 03:36 > To: Vlim <v...@gigadevice.com>; Nikolai Artemiev <nartem...@google.com>; > flashrom@flashrom.org <flashrom@flashrom.org>; Peter Marheine > <pmarhe...@chromium.org> > Subject: Re: [flashrom] Re: adding part # > > 此为外部邮件，谨防钓鱼邮件，请注意邮件是否涉及敏感信息 > This is an external email, beware of phishing emails. Please pay close > attention to whether the email contains sensitive information > You need to be logged into your Github account, and then open Gerrit login > link and click "GitHub OAuth2". > > On Thu, Apr 18, 2024 at 3:33 PM Vlim <v...@gigadevice.com> wrote: > > Hi, Anastasia, > > Looks like I am not able to create an account on > https://review.coreboot.org/login > > This is what I got. And the account I have created on Github. > > Regards, > > Victor > > > victor@victor-0-1:~/Desktop/flashrom$ git push upstream HEAD:refs/for/main > Username for 'https://review.coreboot.org': victorswlim1 > Password for 'https://victorswl...@review.coreboot.org': > remote: Unauthorized > fatal: Authentication failed for 'https://review.coreboot.org/flashrom/' > > > > ________________________________ > From: Anastasia Klimchuk <a...@chromium.org> > Sent: Wednesday, April 17, 2024 21:50 > To: Vlim <v...@gigadevice.com>; Nikolai Artemiev <nartem...@google.com>; > flashrom@flashrom.org <flashrom@flashrom.org>; Peter Marheine > <pmarhe...@chromium.org> > Subject: Re: [flashrom] Re: adding part # > > 此为外部邮件，谨防钓鱼邮件，请注意邮件是否涉及敏感信息 > This is an external email, beware of phishing emails. Please pay close > attention to whether the email contains sensitive information > > It seems like you created a commit locally, that's good! > Next instructions are to push your patch to Gerrit, here: > https://apc01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fflashrom.org%2Fdev_guide%2Fdevelopment_guide.html%23working-with-gerrit-1&data=05%7C02%7Cvlim%40gigadevice.com%7C0b09f658b282474a853f08dc5f631fbd%7Cf84ba339959c4ab19b671e43414f945e%7C0%7C0%7C638490126569576897%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=jepI7tFHfjvtk4sWqS00gM9HXv3tq4f6o4%2FelRZWVFM%3D&reserved=0 > > On Thu, Apr 18, 2024 at 2:13 PM Vlim <v...@gigadevice.com> wrote: > > > > Hi, Anastasia, > > > > I am a little lost. Can you advise I should do next. > > I am getting to the following step. > > > > Regards, > > > > Victor > > > > > > victor@victor-0-1:~/Desktop/flashrom$ git commit -a -s > > [upstream/main 4b717ed3] <Flashrom SPI NOR>: adding a few new SPI NOR part > > numbers > > 2 files changed, 742 insertions(+), 24 deletions(-) > > victor@victor-0-1:~/Desktop/flashrom$ git log > > commit 4b717ed35f72c4dd460d97d030670f8b5b07efb4 (HEAD -> upstream/main) > > Author: Victor Lim <v...@gigadevice.com> > > Date: Wed Apr 17 20:53:44 2024 -0700 > > > > <Flashrom SPI NOR>: adding a few new SPI NOR part numbers > > > > These are the part # added > > GD25LB128E: 1.8V 128Mbit QE = 1 > > GD25LQ128E: 1.8V 128Mbit > > GD25LR128E: 1.8V 128Mbit RPMC > > GD25LB256F: 1.8V 256Mbit QE = 1 > > GD25LQ256H: 1.8V 256Mbit > > GD25LR256F: 1.8V 256Mbit RPMC > > GD25LB512MF: 1.8V 512Mbit QE = 1 > > GD25LR512MF: 1.8V 512Mbit RPMC > > GD25LF128E: 1.8V 128Mbit > > GD25LF256F: 1.8V 256Mbit > > GD25LF512MF: 1.8V 512Mbit > > GD25LB256E: 1.8V 256Mbit QE = 1 > > GD25LB512ME: 1.8V 512Mbit QE = 1 > > GD25B128E: 3V 128Mbit QE = 1 > > GD25Q128E: 3V 128Mbit > > GD25R128E: 3V 128Mbit RPMC > > GD25B256E: 3V 256Mbit QE = 1 > > GD25Q256E: 3V 256Mbit > > GD25R256E: 3V 256Mbit RPMC > > GD25B512MF: 3V 512Mbit QE = 1 > > GD25R512MF: 3V 512Mbit RPMC > > GD25F64F: 3V 64Mbit > > GD25F128F: 3V 128Mbit > > GD25F256F: 3V 256Mbit > > GD25F512MF: 3V 512Mbit > > GD25B512ME: 3V 512Mbit QE = 1 > > > > Change-Id: I1526eed830845d5391ca14c7fd3ac58a5aee71f2 > > Signed-off-by: Victor Lim <v...@gigadevice.com> > > > > commit 041644a6afb12232495c45d3450ae0b3e2eb2a2d (origin/main, origin/HEAD, > > main) > > Author: Hsuan Ting Chen <roccoc...@google.com> > > :...skipping... > > commit 4b717ed35f72c4dd460d97d030670f8b5b07efb4 (HEAD -> upstream/main) > > Author: Victor Lim <v...@gigadevice.com> > > Date: Wed Apr 17 20:53:44 2024 -0700 > > > > <Flashrom SPI NOR>: adding a few new SPI NOR part numbers > > > > These are the part # added > > GD25LB128E: 1.8V 128Mbit QE = 1 > > GD25LQ128E: 1.8V 128Mbit > > GD25LR128E: 1.8V 128Mbit RPMC > > GD25LB256F: 1.8V 256Mbit QE = 1 > > GD25LQ256H: 1.8V 256Mbit > > GD25LR256F: 1.8V 256Mbit RPMC > > GD25LB512MF: 1.8V 512Mbit QE = 1 > > GD25LR512MF: 1.8V 512Mbit RPMC > > GD25LF128E: 1.8V 128Mbit > > GD25LF256F: 1.8V 256Mbit > > GD25LF512MF: 1.8V 512Mbit > > GD25LB256E: 1.8V 256Mbit QE = 1 > > GD25LB512ME: 1.8V 512Mbit QE = 1 > > GD25B128E: 3V 128Mbit QE = 1 > > GD25Q128E: 3V 128Mbit > > GD25R128E: 3V 128Mbit RPMC > > GD25B256E: 3V 256Mbit QE = 1 > > GD25Q256E: 3V 256Mbit > > GD25R256E: 3V 256Mbit RPMC > > GD25B512MF: 3V 512Mbit QE = 1 > > GD25R512MF: 3V 512Mbit RPMC > > GD25F64F: 3V 64Mbit > > GD25F128F: 3V 128Mbit > > GD25F256F: 3V 256Mbit > > GD25F512MF: 3V 512Mbit > > GD25B512ME: 3V 512Mbit QE = 1 > > > > Change-Id: I1526eed830845d5391ca14c7fd3ac58a5aee71f2 > > Signed-off-by: Victor Lim <v...@gigadevice.com> > > > > commit 041644a6afb12232495c45d3450ae0b3e2eb2a2d (origin/main, origin/HEAD, > > main) > > Author: Hsuan Ting Chen <roccoc...@google.com> > > Date: Thu Mar 7 18:46:10 2024 +0800 > > :...skipping... > > commit 4b717ed35f72c4dd460d97d030670f8b5b07efb4 (HEAD -> upstream/main) > > Author: Victor Lim <v...@gigadevice.com> > > Date: Wed Apr 17 20:53:44 2024 -0700 > > > > <Flashrom SPI NOR>: adding a few new SPI NOR part numbers > > > > These are the part # added > > GD25LB128E: 1.8V 128Mbit QE = 1 > > GD25LQ128E: 1.8V 128Mbit > > GD25LR128E: 1.8V 128Mbit RPMC > > GD25LB256F: 1.8V 256Mbit QE = 1 > > GD25LQ256H: 1.8V 256Mbit > > GD25LR256F: 1.8V 256Mbit RPMC > > GD25LB512MF: 1.8V 512Mbit QE = 1 > > GD25LR512MF: 1.8V 512Mbit RPMC > > GD25LF128E: 1.8V 128Mbit > > GD25LF256F: 1.8V 256Mbit > > GD25LF512MF: 1.8V 512Mbit > > GD25LB256E: 1.8V 256Mbit QE = 1 > > GD25LB512ME: 1.8V 512Mbit QE = 1 > > GD25B128E: 3V 128Mbit QE = 1 > > GD25Q128E: 3V 128Mbit > > GD25R128E: 3V 128Mbit RPMC > > GD25B256E: 3V 256Mbit QE = 1 > > GD25Q256E: 3V 256Mbit > > GD25R256E: 3V 256Mbit RPMC > > GD25B512MF: 3V 512Mbit QE = 1 > > GD25R512MF: 3V 512Mbit RPMC > > GD25F64F: 3V 64Mbit > > GD25F128F: 3V 128Mbit > > GD25F256F: 3V 256Mbit > > GD25F512MF: 3V 512Mbit > > GD25B512ME: 3V 512Mbit QE = 1 > > > > Change-Id: I1526eed830845d5391ca14c7fd3ac58a5aee71f2 > > Signed-off-by: Victor Lim <v...@gigadevice.com> > > > > commit 041644a6afb12232495c45d3450ae0b3e2eb2a2d (origin/main, origin/HEAD, > > main) > > Author: Hsuan Ting Chen <roccoc...@google.com> > > Date: Thu Mar 7 18:46:10 2024 +0800 > > > > :...skipping... > > commit 4b717ed35f72c4dd460d97d030670f8b5b07efb4 (HEAD -> upstream/main) > > Author: Victor Lim <v...@gigadevice.com> > > Date: Wed Apr 17 20:53:44 2024 -0700 > > > > <Flashrom SPI NOR>: adding a few new SPI NOR part numbers > > > > These are the part # added > > GD25LB128E: 1.8V 128Mbit QE = 1 > > GD25LQ128E: 1.8V 128Mbit > > GD25LR128E: 1.8V 128Mbit RPMC > > GD25LB256F: 1.8V 256Mbit QE = 1 > > GD25LQ256H: 1.8V 256Mbit > > GD25LR256F: 1.8V 256Mbit RPMC > > GD25LB512MF: 1.8V 512Mbit QE = 1 > > GD25LR512MF: 1.8V 512Mbit RPMC > > GD25LF128E: 1.8V 128Mbit > > GD25LF256F: 1.8V 256Mbit > > GD25LF512MF: 1.8V 512Mbit > > GD25LB256E: 1.8V 256Mbit QE = 1 > > GD25LB512ME: 1.8V 512Mbit QE = 1 > > GD25B128E: 3V 128Mbit QE = 1 > > GD25Q128E: 3V 128Mbit > > GD25R128E: 3V 128Mbit RPMC > > GD25B256E: 3V 256Mbit QE = 1 > > GD25Q256E: 3V 256Mbit > > GD25R256E: 3V 256Mbit RPMC > > GD25B512MF: 3V 512Mbit QE = 1 > > GD25R512MF: 3V 512Mbit RPMC > > GD25F64F: 3V 64Mbit > > GD25F128F: 3V 128Mbit > > GD25F256F: 3V 256Mbit > > GD25F512MF: 3V 512Mbit > > GD25B512ME: 3V 512Mbit QE = 1 > > > > Change-Id: I1526eed830845d5391ca14c7fd3ac58a5aee71f2 > > Signed-off-by: Victor Lim <v...@gigadevice.com> > > > > commit 041644a6afb12232495c45d3450ae0b3e2eb2a2d (origin/main, origin/HEAD, > > main) > > Author: Hsuan Ting Chen <roccoc...@google.com> > > Date: Thu Mar 7 18:46:10 2024 +0800 > > > > classic_cli_manpage.rst: Update doc for custom_rst of raiden_debug_spi > > :...skipping... > > commit 4b717ed35f72c4dd460d97d030670f8b5b07efb4 (HEAD -> upstream/main) > > Author: Victor Lim <v...@gigadevice.com> > > Date: Wed Apr 17 20:53:44 2024 -0700 > > > > <Flashrom SPI NOR>: adding a few new SPI NOR part numbers > > > > These are the part # added > > GD25LB128E: 1.8V 128Mbit QE = 1 > > GD25LQ128E: 1.8V 128Mbit > > GD25LR128E: 1.8V 128Mbit RPMC > > GD25LB256F: 1.8V 256Mbit QE = 1 > > GD25LQ256H: 1.8V 256Mbit > > GD25LR256F: 1.8V 256Mbit RPMC > > GD25LB512MF: 1.8V 512Mbit QE = 1 > > GD25LR512MF: 1.8V 512Mbit RPMC > > GD25LF128E: 1.8V 128Mbit > > GD25LF256F: 1.8V 256Mbit > > GD25LF512MF: 1.8V 512Mbit > > GD25LB256E: 1.8V 256Mbit QE = 1 > > GD25LB512ME: 1.8V 512Mbit QE = 1 > > GD25B128E: 3V 128Mbit QE = 1 > > GD25Q128E: 3V 128Mbit > > GD25R128E: 3V 128Mbit RPMC > > GD25B256E: 3V 256Mbit QE = 1 > > GD25Q256E: 3V 256Mbit > > GD25R256E: 3V 256Mbit RPMC > > GD25B512MF: 3V 512Mbit QE = 1 > > GD25R512MF: 3V 512Mbit RPMC > > GD25F64F: 3V 64Mbit > > GD25F128F: 3V 128Mbit > > GD25F256F: 3V 256Mbit > > GD25F512MF: 3V 512Mbit > > GD25B512ME: 3V 512Mbit QE = 1 > > > > Change-Id: I1526eed830845d5391ca14c7fd3ac58a5aee71f2 > > Signed-off-by: Victor Lim <v...@gigadevice.com> > > > > commit 041644a6afb12232495c45d3450ae0b3e2eb2a2d (origin/main, origin/HEAD, > > main) > > Author: Hsuan Ting Chen <roccoc...@google.com> > > Date: Thu Mar 7 18:46:10 2024 +0800 > > > > classic_cli_manpage.rst: Update doc for custom_rst of raiden_debug_spi > > > > :...skipping... > > commit 4b717ed35f72c4dd460d97d030670f8b5b07efb4 (HEAD -> upstream/main) > > Author: Victor Lim <v...@gigadevice.com> > > Date: Wed Apr 17 20:53:44 2024 -0700 > > > > <Flashrom SPI NOR>: adding a few new SPI NOR part numbers > > > > These are the part # added > > GD25LB128E: 1.8V 128Mbit QE = 1 > > GD25LQ128E: 1.8V 128Mbit > > GD25LR128E: 1.8V 128Mbit RPMC > > GD25LB256F: 1.8V 256Mbit QE = 1 > > GD25LQ256H: 1.8V 256Mbit > > GD25LR256F: 1.8V 256Mbit RPMC > > GD25LB512MF: 1.8V 512Mbit QE = 1 > > GD25LR512MF: 1.8V 512Mbit RPMC > > GD25LF128E: 1.8V 128Mbit > > GD25LF256F: 1.8V 256Mbit > > GD25LF512MF: 1.8V 512Mbit > > GD25LB256E: 1.8V 256Mbit QE = 1 > > GD25LB512ME: 1.8V 512Mbit QE = 1 > > GD25B128E: 3V 128Mbit QE = 1 > > GD25Q128E: 3V 128Mbit > > GD25R128E: 3V 128Mbit RPMC > > GD25B256E: 3V 256Mbit QE = 1 > > GD25Q256E: 3V 256Mbit > > GD25R256E: 3V 256Mbit RPMC > > GD25B512MF: 3V 512Mbit QE = 1 > > GD25R512MF: 3V 512Mbit RPMC > > GD25F64F: 3V 64Mbit > > GD25F128F: 3V 128Mbit > > GD25F256F: 3V 256Mbit > > GD25F512MF: 3V 512Mbit > > GD25B512ME: 3V 512Mbit QE = 1 > > > > Change-Id: I1526eed830845d5391ca14c7fd3ac58a5aee71f2 > > Signed-off-by: Victor Lim <v...@gigadevice.com> > > > > commit 041644a6afb12232495c45d3450ae0b3e2eb2a2d (origin/main, origin/HEAD, > > main) > > Author: Hsuan Ting Chen <roccoc...@google.com> > > Date: Thu Mar 7 18:46:10 2024 +0800 > > > > classic_cli_manpage.rst: Update doc for custom_rst of raiden_debug_spi > > > > Update technical details for custom_rst of raiden_debug_spi to help > > users better understand their configuration options. > > > > BUG=b:161745002 > > BRANCH=none > > : > > > > > > > > ________________________________ > > From: Anastasia Klimchuk <a...@chromium.org> > > Sent: Saturday, April 13, 2024 00:19 > > To: Vlim <v...@gigadevice.com>; Nikolai Artemiev <nartem...@google.com>; > > Peter Marheine <pmarhe...@chromium.org>; flashrom@flashrom.org > > <flashrom@flashrom.org> > > Subject: Re: [flashrom] Re: adding part # > > > > 此为外部邮件，谨防钓鱼邮件，请注意邮件是否涉及敏感信息 > > This is an external email, beware of phishing emails. Please pay close > > attention to whether the email contains sensitive information > > > > This is really good news! I am so glad to hear that you are almost > > there. Thank you for your effort! > > > > We have the advice and instructions documented in Development Guide > > here: > > https://apc01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fflashrom.org%2Fdev_guide%2Fdevelopment_guide.html&data=05%7C02%7Cvlim%40gigadevice.com%7C0b09f658b282474a853f08dc5f631fbd%7Cf84ba339959c4ab19b671e43414f945e%7C0%7C0%7C638490126569587392%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=7O1sb0%2B7iS%2BcStfV7X%2FKKYSQDj2vgqec8LQS%2BhVh32g%3D&reserved=0 > > And maybe you read this doc already, but if not, it's a good time to > > read it before pushing a patch. > > > > On Sat, Apr 13, 2024 at 3:46 AM Vlim <v...@gigadevice.com> wrote: > > > > > > Hi, Anastasia, > > > > > > It was due to the ch341a_spi not stable after my modification. > > > The on-board controller was powered by a 5V supply, and output signals > > > are 5V. > > > I changed the power to 3V, since then, it was not stable sometimes. > > > After adding a cap to the 3V line close to the controller, it is ok now. > > > > > > I have almost finished verification for the new part #s to be added. > > > Expecting to submit the patch in a few days. > > > Do you have any advice for me about submitting the patch? > > > > > > Files I have modified are Flashchip.c and .h. > > > > > > Regards, > > > > > > Victor > > > > > > ________________________________ > > > From: Anastasia Klimchuk <a...@chromium.org> > > > Sent: Friday, April 12, 2024 02:25 > > > To: Vlim <v...@gigadevice.com>; Nikolai Artemiev <nartem...@google.com>; > > > flashrom@flashrom.org <flashrom@flashrom.org>; Peter Marheine > > > <pmarhe...@chromium.org> > > > Subject: Re: [flashrom] Re: adding part # > > > > > > 此为外部邮件，谨防钓鱼邮件，请注意邮件是否涉及敏感信息 > > > This is an external email, beware of phishing emails. Please pay close > > > attention to whether the email contains sensitive information > > > > > > This looks like timeout might be happening because of how your > > > programmer device is set up, not necessarily because the chip > > > definition is wrong. I remember often people say about ch341a_spi > > > "check the wires are not too long", maybe this applies to you? > > > > > > Also, you need to give more info: > > > > > > the exact command you ran > > > and full verbose logs (-VVV gives you super verbose mode) > > > also what are your current local changes? I assume you run it on your > > > local commit? you can push a patch and mark it "work in progress" so > > > that we know what is the actual code that you are running. > > > > > > On Tue, Apr 9, 2024 at 3:04 PM Vlim <v...@gigadevice.com> wrote: > > > > > > > > Thanks. > > > > > > > > Another question. > > > > I am getting the following message, please advise what is the possible > > > > issue? > > > > > > > > Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). > > > > Found GigaDevice flash chip "GD25F64F" (8192 kB, SPI) on ch341a_spi. > > > > Reading old flash chip contents... done. > > > > > > > > cb_in: error: LIBUSB_TRANSFER_TIMED_OUT > > > > ch341a_spi_spi_send_command: Failed to read 3 bytes > > > > Register read failed! > > > > write_flash: failed to write (0x66b200..0x66b7ff). > > > > Write failed at 0x5, Abort. > > > > Erase/write done from 0 to 7fffff > > > > Write Failed!Uh oh. Erase/write failed. Checking if anything has > > > > changed. > > > > Reading current flash chip contents... > > > > cb_out: error: LIBUSB_TRANSFER_TIMED_OUT > > > > > > > > cb_in: error: LIBUSB_TRANSFER_TIMED_OUT > > > > > > > > cb_in: error: LIBUSB_TRANSFER_TIMED_OUT > > > > > > > > Regards, > > > > > > > > Victor > > > > > > > > ________________________________ > > > > From: Anastasia Klimchuk <a...@chromium.org> > > > > Sent: Monday, April 8, 2024 06:00 > > > > To: Vlim <v...@gigadevice.com>; Nikolai Artemiev > > > > <nartem...@google.com>; flashrom@flashrom.org <flashrom@flashrom.org>; > > > > Peter Marheine <pmarhe...@chromium.org> > > > > Subject: Re: [flashrom] Re: adding part # > > > > > > > > 此为外部邮件，谨防钓鱼邮件，请注意邮件是否涉及敏感信息 > > > > This is an external email, beware of phishing emails. Please pay close > > > > attention to whether the email contains sensitive information > > > > > > > > If I understand your question correctly, `–wp-status` command should > > > > give you the info: > > > > Prints the flash’s current status register protection mode and write > > > > protection range. > > > > > > > > Probably you have looked at that already, but just in case all > > > > available commands are in the man page, or also can be read here: > > > > https://apc01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fflashrom.org%2Fclassic_cli_manpage.html&data=05%7C02%7Cvlim%40gigadevice.com%7C0b09f658b282474a853f08dc5f631fbd%7Cf84ba339959c4ab19b671e43414f945e%7C0%7C0%7C638490126569593124%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=HlypbyXESW84qzLdECD7tOKT%2F0iXOHx9lbCUBb6lCj0%3D&reserved=0 > > > > > > > > > > > > On Sun, Apr 7, 2024 at 7:55 AM Vlim <v...@gigadevice.com> wrote: > > > > > > > > > > Looked at it further and understood that it is determined by the BPx > > > > > bits, tb bit. > > > > > Is there a way I can read the status registers to make sure that all > > > > > these bits match with the datasheet? > > > > > > > > > > Regards, > > > > > > > > > > Victor > > > > > > > > > > > > > > > ________________________________ > > > > > From: Vlim <v...@gigadevice.com> > > > > > Sent: Friday, April 5, 2024 20:37 > > > > > To: Nikolai Artemiev <nartem...@google.com>; Anastasia Klimchuk > > > > > <a...@chromium.org> > > > > > Cc: flashrom@flashrom.org <flashrom@flashrom.org>; Peter Marheine > > > > > <pmarhe...@chromium.org> > > > > > Subject: Re: [flashrom] Re: adding part # > > > > > > > > > > Thanks. > > > > > > > > > > How are the protection ranges defined? > > > > > My device has ½ to 1/512. > > > > > So I am missing 1/128, 1/256, 1/512. > > > > > And I am getting some extra from 1/1024 to 1/8192. > > > > > > > > > > Please advise. > > > > > > > > > > Regards, > > > > > > > > > > Victor > > > > > > > > > > > > > > > > > > > > ________________________________ > > > > > From: Nikolai Artemiev <nartem...@google.com> > > > > > Sent: Tuesday, March 26, 2024 18:54 > > > > > To: Anastasia Klimchuk <a...@chromium.org> > > > > > Cc: Vlim <v...@gigadevice.com>; flashrom@flashrom.org > > > > > <flashrom@flashrom.org>; Peter Marheine <pmarhe...@chromium.org> > > > > > Subject: Re: [flashrom] Re: adding part # > > > > > > > > > > You don't often get email from nartem...@google.com. Learn why this > > > > > is important > > > > > 此为外部邮件，谨防钓鱼邮件，请注意邮件是否涉及敏感信息 > > > > > This is an external email, beware of phishing emails. Please pay > > > > > close attention to whether the email contains sensitive information > > > > > Hi Victor, > > > > > > > > > > One thing to note with the printlock and unlock functions you > > > > > mentioned earlier, i.e.: > > > > > > > > > > .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, > > > > > .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, > > > > > > > > > > These functions basically just allow flashrom to remove memory > > > > > protection before writing to the chip. They can (and should) be > > > > > omitted if you define reg_bits and decode_range in the chip entry, > > > > > because that will enable full writeprotect support for the chip. > > > > > > > > > > The reason we still have unlock and printlock functions is for older > > > > > chips that don't have reg_bits and decode_range defined. > > > > > > > > > > Cheers, > > > > > Nik > > > > > > > > > > > > > > > > > > > > On Tue, Mar 26, 2024 at 4:32 PM Anastasia Klimchuk > > > > > <a...@chromium.org> wrote: > > > > > > > > > > I will try to answer to everything in one message, but feel free to > > > > > ask more questions > > > > > > > > > > > Can you point me to the file that defines the commands? > > > > > > > > > > Most of them will be in include/spi.h > > > > > > > > > > It is a longer way if you want to trace implementation from, for > > > > > example SPI_CHIP_READ, to the place where command is sent, but in case > > > > > you would need it: > > > > > > > > > > you would need to go through the sequence of function calls, starting > > > > > from `spi_chip_read` in spi.c and then look into the programmer code > > > > > (for whichever is the programmer you are using) and see how that > > > > > programmer implements spi read and send commands. Specifically look > > > > > for `static const struct spi_master` in the programmer source code > > > > > file. > > > > > > > > > > Default functions are in spi.c and spi25.c files. > > > > > > > > > > > How is Dual IO and Quad IO supported here? > > > > > > > > > > Currently not implemented, however it would be really great to > > > > > implement it in the future (contributions are very welcome). > > > > > We do have those aspirational comments in flashchips.c , for example > > > > > (I am just copying from some chip) > > > > > > > > > > .write = SPI_CHIP_WRITE256, /* Dual I/O (0xA2) supported */ > > > > > .read = SPI_CHIP_READ, /* Fast read (0x0B), dual I/O (0x3B) > > > > > supported */ > > > > > > > > > > So maybe you can add similar comments for the chip definition for now. > > > > > > > > > > On Tue, Mar 26, 2024 at 5:27 AM Vlim <v...@gigadevice.com> wrote: > > > > > > > > > > > > Hi, > > > > > > > > > > > > Can you point me to the file that defines the commands? > > > > > > Like SPI_CHIP_READ being 0x0b. > > > > > > > > > > > > Thanks, > > > > > > > > > > > > Victor > > > > > > > > > > > > ________________________________ > > > > > > From: Anastasia Klimchuk <a...@chromium.org> > > > > > > Sent: Thursday, March 21, 2024 23:32 > > > > > > To: Vlim <v...@gigadevice.com>; flashrom@flashrom.org > > > > > > <flashrom@flashrom.org> > > > > > > Cc: Peter Marheine <pmarhe...@chromium.org> > > > > > > Subject: Re: [flashrom] Re: adding part # > > > > > > > > > > > > [You don't often get email from a...@chromium.org. Learn why this > > > > > > is important at https://aka.ms/LearnAboutSenderIdentification ] > > > > > > > > > > > > 此为外部邮件，谨防钓鱼邮件，请注意邮件是否涉及敏感信息 > > > > > > This is an external email, beware of phishing emails. Please pay > > > > > > close attention to whether the email contains sensitive information > > > > > > > > > > > > For these two (printlock and unlock), you need to pick the function > > > > > > which handles the highest BP bit that chip supports. In your > > > > > > example, > > > > > > if a chip supports bits BP0-BP4 the correct functions are those with > > > > > > BP4 in the name. So you did it all right. > > > > > > > > > > > > If the chip supports write protection, you also need to set > > > > > > .reg_bits > > > > > > in chip definition. For this you need to have a look at struct > > > > > > reg_bit_map in include/flash.h, it has comments on what each bit in > > > > > > the struct means. > > > > > > > > > > > > > > > > > > On Fri, Mar 22, 2024 at 7:22 AM Vlim <v...@gigadevice.com> wrote: > > > > > > > > > > > > > > Thanks, Anastasia, > > > > > > > > > > > > > > Can you please explain this statement, > > > > > > > > > > > > > > .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, > > > > > > > .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, > > > > > > > > > > > > > > Looks like this is to support memory array protection. But it > > > > > > > needs BP0-BP4. > > > > > > > Do I need to specify BP0 to BP3 as well? > > > > > > > Or I specify the setting when I initiate the flashrom programming > > > > > > > command? > > > > > > > > > > > > > > Regards, > > > > > > > > > > > > > > Victor > > > > > > > > > > > > > > ________________________________ > > > > > > > From: Anastasia Klimchuk <a...@chromium.org> > > > > > > > Sent: Thursday, March 21, 2024 05:32 > > > > > > > To: Vlim <v...@gigadevice.com>; flashrom@flashrom.org > > > > > > > <flashrom@flashrom.org> > > > > > > > Cc: Peter Marheine <pmarhe...@chromium.org> > > > > > > > Subject: [flashrom] Re: adding part # > > > > > > > > > > > > > > You don't often get email from a...@chromium.org. Learn why this > > > > > > > is important > > > > > > > 此为外部邮件，谨防钓鱼邮件，请注意邮件是否涉及敏感信息 > > > > > > > This is an external email, beware of phishing emails. Please pay > > > > > > > close attention to whether the email contains sensitive > > > > > > > information > > > > > > > Hello Victor, > > > > > > > > > > > > > > Various feature bits are defined as macros in include/flash.h , > > > > > > > some of them have comments explaining what they do. If the > > > > > > > feature name is not descriptive, and there is no comment, but you > > > > > > > think you might need this feature: feel free to ask. I would try > > > > > > > to add comments later. > > > > > > > > > > > > > > SPI_DISABLE_BLOCKPROTECT_BP4_SRWD and other unlock functions as > > > > > > > in spi25_statusreg.c. Those functions have comments, hopefully > > > > > > > this can help! > > > > > > > > > > > > > > On Thu, Mar 21, 2024 at 2:48 PM Vlim <v...@gigadevice.com> wrote: > > > > > > > > > > > > > > Thanks, Peter, > > > > > > > > > > > > > > Where can I find the definition of terms like, > > > > > > > > > > > > > > .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | > > > > > > > FEATURE_WRSR_EXT2, > > > > > > > SPI_DISABLE_BLOCKPROTECT_BP4_SRWD > > > > > > > > > > > > > > Regards, > > > > > > > > > > > > > > Victor > > > > > > > > > > > > > > > > > > > > > ________________________________ > > > > > > > From: Peter Marheine <pmarhe...@chromium.org> > > > > > > > Sent: Tuesday, March 19, 2024 15:42 > > > > > > > To: Vlim <v...@gigadevice.com> > > > > > > > Cc: flashrom@flashrom.org <flashrom@flashrom.org> > > > > > > > Subject: Re: [flashrom] adding part # > > > > > > > > > > > > > > You don't often get email from pmarhe...@chromium.org. Learn why > > > > > > > this is important > > > > > > > 此为外部邮件，谨防钓鱼邮件，请注意邮件是否涉及敏感信息 > > > > > > > This is an external email, beware of phishing emails. Please pay > > > > > > > close attention to whether the email contains sensitive > > > > > > > information > > > > > > > Our "how to add a new chip" documentation should point you in the > > > > > > > right direction: > > > > > > > https://apc01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fflashrom.org%2Fcontrib_howtos%2Fhow_to_add_new_chip.html&data=05%7C02%7Cvlim%40gigadevice.com%7C0b09f658b282474a853f08dc5f631fbd%7Cf84ba339959c4ab19b671e43414f945e%7C0%7C0%7C638490126569597745%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=EEkWr%2BOhSFp%2FNUh2gbxxnEbeDhLVm5KT7O4cw3iZVrU%3D&reserved=0 > > > > > > > > > > > > > > But feel free to ask further questions if anything there doesn't > > > > > > > seem sufficient for your needs. > > > > > > > > > > > > > > On Wed, Mar 20, 2024 at 6:31 AM Vlim <v...@gigadevice.com> wrote: > > > > > > > > > > > > > > Hi, FlashRom team, > > > > > > > > > > > > > > I am the FAE director in Gigadevice and I would like to add some > > > > > > > part #s to the flashchip.c and flashchip.h. > > > > > > > Can you please provide some guidance? > > > > > > > > > > > > > > Regards, > > > > > > > > > > > > > > Victor Lim > > > > > > > FAE Director > > > > > > > GigaDevice Semiconductor > > > > > > > 4088833856 > > > > > > > > > > > > > > _______________________________________________ > > > > > > > flashrom mailing list -- flashrom@flashrom.org > > > > > > > To unsubscribe send an email to flashrom-le...@flashrom.org > > > > > > > > > > > > > > _______________________________________________ > > > > > > > flashrom mailing list -- flashrom@flashrom.org > > > > > > > To unsubscribe send an email to flashrom-le...@flashrom.org > > > > > > > > > > > > > > > > > > > > > > > > > > > > -- > > > > > > > Anastasia. > > > > > > > > > > > > > > > > > > > > > > > > -- > > > > > > Anastasia. > > > > > > > > > > > > > > > > > > > > -- > > > > > Anastasia. > > > > > _______________________________________________ > > > > > flashrom mailing list -- flashrom@flashrom.org > > > > > To unsubscribe send an email to flashrom-le...@flashrom.org > > > > > > > > > > > > > > > > -- > > > > Anastasia. > > > > > > > > > > > > -- > > > Anastasia. > > > > > > > > -- > > Anastasia. > > > > -- > Anastasia. > > > > -- > Anastasia. -- Anastasia. _______________________________________________ flashrom mailing list -- flashrom@flashrom.org To unsubscribe send an email to flashrom-le...@flashrom.org
