Nate,
I am wondering what work is being done/planned for targeting FPGA
platforms.
We have lots of desires in this direction, but no concrete plans.
Several people in our group are interested in FPGAs and own small
experimenter's boards. We keep an eye on developments (notably the
BEE3) and spend some time tinkering with our smaller boards, but lack
expertise and manpower to do anything serious. If we did have
expertise and resources we'd probably be looking at new hardware
architectures that are optimised for the structures at the lowest
level of our software architecture and at targeting FPGAs the same
way we target off-the-shelf CPUs.
Alan once said that hardware is just software crystalised early (or
something similar) and I think that echoes the instincts of many
people in this group.
My interests overlap with this field, and I would like to
contribute towards such an effort.
I'd love to see somebody figure out how to dynamically generate bit
files from an intermediate representation (Jolt ASTs, for example) to
allow reprogramming of the hardware on the fly. (My memory is
terrible but I think Hans-Martin Mosner was interested in this and
maybe even making headway.) It would be a lot of fun to use this to
make self-modifying hardware. Chuck Thacker has designed a very
simple CPU (three pages of verilog) that could be a 'traditional'
target CPU for our ASTs, letting us bring up the dynamic netlist
generation and hence a fully self-modifying environment on FPGA.
Again, we lack expertise in this area and don't really even know how
feasible it is for these devices to address their own LUTs and
reprogram themselves selectively on the fly.
I have experience with quite a few "non traditional" HDLs, and
would like to help OMeta to grow into the first "meta" design
language.
We would love to see this happen too, and can offer encouragement and
consultation as and when you need them.
Regards,
Ian
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