[t13] Shall the ATA device interrupt for each DRQ block transferred even though nIEN bit of the Device Control register is 1?

[kepler]

This message is from the T13 list server.


In clause 8.59.8, page 289 of ATA/ATAPI-6, it describes that "The device
shall interrupt for each DRQ block transferred" for the WRITE LOG EXT
command.
However, there is not prerequisite to clear nIEN bit in the Device
Control register. If the nIEN bit is not previously cleared, shall INTRQ
still be asserted after each DRQ block?

Kepler