Joel,
there is no test point placement in schematic. What are you using
for test points, the automated testpoint function in PCB? If you are then
there is definitely no equivalent function in the schematic and you would
probably want only a drawn/text item (not a symbol w/ part association) to
indicate the location of the test point in the schematic. In our company we
simply have made a testpoint symbol which calls up a testpoint pad footprint
in PCB. We place the testpoints manually where we want it.
This also brings to mind a question for all. Do most of you use the
PCB testpoint selection function or place your own solid pad testpoints?
What is the current common philosophy regarding using vias for testpoints?
It used to be that a fair number of people said not to use existing vias
because of the possibility of damage to the vias, i.e. cracks between the
barrels and pad. Any articles or sources to back this up?
Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com
> -----Original Message-----
> From: Joel Hammer [mailto:[EMAIL PROTECTED]]
> Sent: Monday, June 25, 2001 7:22 AM
> To: Protel EDA Forum
> Subject: [PEDA] placing a test point in a schematic
>
>
> do i have to create a test point schematic symbol or is there
> a "place, test
> point" or similar function? i'm almost sure it is the later.
> but i'll be
> da*@%d if i can find it. please help.
>
> thanks
> joel
>
> Joel L. Hammer
> PCB Design / AutoCad Specialist
> E2 Enterprises Inc.
> 636.949.9101 Ext. 26
> www.e2enterprises.com
>
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