Op Thu, 28 Feb 2008, schreef Michael Schnell:
Nonetheless the count of word transfers form memory to/from the cache would be smaller with packed records which might result in a lot faster execution (of course depending on the layout of the record, speed of the memory, speed of the processor, type of operations done with the records, ...)An ARM does not have such logic and will suffer cache miss after cache miss.
That is exactly what I wanted to explain: even on ARM the lower amount of cache misses might pay for the (higher) cost of an unaligned load.
Daniël
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