Thank you Sergei, I will have a look at that code.
I have just finished inserting ugly .long 0xxxxxx statements in my code
to hardcode the missing pieces, I am really glad you answered ;-) ;-)
I also found some statements that get translated wrong:
and $a0,$a0,0
and $a1,$a1,0
li $t2,0
the statements are missing the last param in the generated assembler file:
pic32mx1xxfxxxb.s:87: Error: absolute expression required `li $t2,'
pic32mx1xxfxxxb.s:102: Error: absolute expression required `and $a0,$a0,'
I guess this needs to be fixed in mips/aasmcpu.pas
Michael
Am 28.05.13 21:31, schrieb Sergei Gorelkin:
28.05.2013 22:50, Michael Ring пишет:
I am currently writing/porting startup code for the pic32 chips, the
inline assembler of fpc seems
to lack support for some opcodes, any idea how I can workarround this?
With grep I found for example mtc1 in opcode.inc, but mtc0 is
missing, this opcode is important for
the initialization of the pic32 chips.
Is it easy to implement those missing op-codes in the internal
assembler, if yes, could some
fpc-crack give me a hint on what to change where?
Since assembler reader for MIPS is at a very early stage, adding
opcodes isn't difficult:
1) Add the opcode enum to mips/opcode.inc and its string
representation to mips/strinst.inc.
2) For 'ext' and 'ins' you'll need to add the appropriate overloaded
constructor to taicpu class in mips/aasmcpu.pas (they are going to be
the first opcodes with 4 operands)
3) Modify taicpu.spilling_get_operation_type method (in
mips/aasmcpu.pas) to reflect which operands are read/written by newly
added opcodes.
A more difficult task will be to restrict opcodes to CPU type and
operands to opcodes.
Those are the missing opcodes:
beqz
ehb
ext
ins
mfc0
mtc0
sdbbp
wrpgpr
Note that 'beqz reg,label' is just a shorter representation of 'beq
reg,$zero,label', not a separate opcode (unlike bgtz/bltz/blez/bgez
which are really missing).
Regards,
Sergei
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