I don't have an M1 myself, but according to the data from the thread on
the lazarus mail list, there is a bug in the 3.3.1 asm generator for M1
var pn8: pint8; // pointer signed byte
In the below expression ...(not pn8^)...
"pn8^" is loaded to w0 and sign extended. From this point onwards
operations on the value should be 32 bits (the value has been extended,
and the full 32 bits are later used).
but "not" only affects the lowest 8 bit.
Apparently in 3.2.2 (or was it 3.2.0) there was
mvn w0,w0
If someone can confirm tihs....
-------- Forwarded Message --------
Subject: [Lazarus] fpc bug with M1 [[was: Re: UTF8LengthFast returning
incorrect results on AARCH64 (MacOS)]]
Date: Tue, 28 Dec 2021 22:47:53 +0100
From: Martin Frb via lazarus <laza...@lists.lazarus-ide.org>
Reply-To: Lazarus mailing list <laza...@lists.lazarus-ide.org>
To: laza...@lists.lazarus-ide.org
CC: Martin Frb <laza...@mfriebe.de>
# [43] Result += (pn8^ shr 7) and ((not pn8^) shr 6);
ldr x0,[sp]
ldrsb w0,[x0] # <<<<< sign extend to a 32bit value
(32bit register).
eor w0,w0,#255 # <<<<< But only "not" the lowest 8 bit. That
is wrong. The calculation uses 32 bit at this point
lsr w0,w0,#6
ldr x2,[sp]
ldrsb w2,[x2]
lsr w2,w2,#7
and w0,w2,w0 # <<<<<< here the full 32 bit are used.
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