On 30/03/17 08:00, Mark Morgan Lloyd wrote:
Finally, I suggest that you look at least briefly at
https://en.wikipedia.org/wiki/Vector_Pascal which appears to have some
quite good stuff in it.
Quoting from manual section 5.4.
Future machines like the Larrabee will have considerably wider
SIMD registers, increasing the benefits of SIMD code. But newer chips
also have multiple cores. For these, the recent versions of the Glasgow
Pascal Compiler will parallelise across multiple cores if the arrays
being worked on are of rank 2. The Pascal source code of the program
remains the same independently of whether it is being targeted at a
simple sequential machine, a SIMD machine or a multi-core SIMD machine.
Targeting is done by flags passed to the compiler:
[...]
Two threads are dispatched to process the work using a fork - rejoin
paradigm. The run time library is built on top of pthreads. For a two
core machine, two server threads are initiated at program start up.
These wait on a semaphore until post_job passes them the address of a
procedure and a stack frame context within which the procedure is to be
executed.
--
Mark Morgan Lloyd
markMLl .AT. telemetry.co .DOT. uk
[Opinions above are the author's, not those of his employers or colleagues]
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