https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=265974
Mark Johnston <ma...@freebsd.org> changed:
What |Removed |Added
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Status|New |Open
--- Comment #4 from Mark Johnston <ma...@freebsd.org> ---
I certainly agree with the comment about smr_enter(). On at least arm64,
atomic_add_acq_int()'s acquire semantics apply only to the load; subsequent
loads can be reordered with the store. I believe this is true with LSE atomics
as well as the original LL/SC atomics. I also agree that the code is fine on
Intel since atomic instructions prevent store-load reordering.
Our atomic(9) documentation doesn't really call out this subtlety. We might
have similar bugs elsewhere.
I need to think about smr_poll() a bit more.
> Moreover, smr_poll() absolutely needs a full memory barrier on entry, the
> `atomic_load_acq_int` performed by `smr_poll` aren't sufficient.
The suggested patch adds two barriers to smr_poll_scan() and none to
smr_poll(), is that intentional?
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