On Fri, 30 Jul 1999, Mike Smith wrote:
> > For some video cards (to wit, the voodoo stuff), the MTRRs should be set up as
> > follows
> >
> > write-combining
> > +----------------------------------------------------------+
> > +-------+
> > uncacheable
> >
> > i.e. the two regions have the same starting area, but the small chunk for the
> > registers should be uncacheable. When I try to do this using memconf on my
> > K6-2, it spits the dummy. Is there a work around for this?
>
> The i686 MTRR implementation, at least, doesn't allow UC to overlap WC;
> only Write-back and uncached are allowed to overlap. I don't know what
> the K6's limitations are; you should talk to Brian Feldman about that.
As long as a range isn't exactly the same (base, len being the same), it
allows the change. The question is how does it fail? I let the hardware
decide what to actually do with the registers, but I write them, so...
I need to know where the problem is.
>
> --
> \\ The mind's the standard \\ Mike Smith
> \\ of the man. \\ [EMAIL PROTECTED]
> \\ -- Joseph Merrick \\ [EMAIL PROTECTED]
>
>
>
>
> To Unsubscribe: send mail to [EMAIL PROTECTED]
> with "unsubscribe freebsd-current" in the body of the message
>
Brian Fundakowski Feldman _ __ ___ ____ ___ ___ ___
[EMAIL PROTECTED] _ __ ___ | _ ) __| \
FreeBSD: The Power to Serve! _ __ | _ \._ \ |) |
http://www.FreeBSD.org/ _ |___/___/___/
To Unsubscribe: send mail to [EMAIL PROTECTED]
with "unsubscribe freebsd-current" in the body of the message
