On Thu, Feb 21, 2013 at 12:43:44PM +0000, Alexey Dokuchaev wrote:
> On Thu, Feb 21, 2013 at 05:33:35PM +0900, YongHyeon PYUN wrote:
> > On Wed, Feb 20, 2013 at 06:08:53AM +0000, Alexey Dokuchaev wrote:
> > > $ dmesg | egrep ale\|atphy
> > > ale0: <Atheros AR8121/AR8113/AR8114 PCIe Ethernet> port 0xcc00-0xcc7f mem
> > > 0xfe9c0000-0xfe9fffff irq 17 at device 0.0 on pci2
> > > ale0: 960 Tx FIFO, 1024 Rx FIFO
> > > ale0: Using 1 MSI messages.
> > > ale0: 4GB boundary crossed, switching to 32bit DMA addressing mode.
> > > miibus0: <MII bus> on ale0
> > > atphy0: <Atheros F1 10/100/1000 PHY> PHY 0 on miibus0
> > > atphy0: none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX,
> > > 1000baseT-FDX, 1000baseT-FDX-master, auto, auto-flow
> > >
> > > $ devinfo -rv | grep atphy
> > > atphy0 pnpinfo oui=0xc82e model=0x1 rev=0x9 at phyno=0
> >
> > Hmm, it's still not clear whether the controller is Gigabit or not.
> > Could you try attached patch and let me the output?
>
> ale_flags = 0x00000040
Thanks for the info. Indeed, your controller is AR8121 Gigabit
etherent(L1E). I guess the PHY initialization is not complete.
Would you try attached patch?
>
> ./danfe
Index: sys/dev/ale/if_ale.c
===================================================================
--- sys/dev/ale/if_ale.c (revision 246937)
+++ sys/dev/ale/if_ale.c (working copy)
@@ -406,11 +406,11 @@
CSR_WRITE_2(sc, ALE_GPHY_CTRL,
GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
GPHY_CTRL_PHY_PLL_ON);
- DELAY(1000);
+ DELAY(2000);
CSR_WRITE_2(sc, ALE_GPHY_CTRL,
GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
- DELAY(1000);
+ DELAY(2000);
#define ATPHY_DBG_ADDR 0x1D
#define ATPHY_DBG_DATA 0x1E
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