On 12/11/13 11:12, Kohji Okuno wrote:
Hi,
I think the xHCI host controller driver has a spec violation.
Could you refer to
``Table 126: Offset 0Ch – Link TRB Field Definitions''
in xHCI_Specification_for_USB.pdf(Revision 1.0)?
The following is an excerpt about the CHAIN BIT.
Chain bit (CH). Set to ‘1’ by software to associate this TRB with
the next TRB on the Ring. A Transfer Descriptor (TD) is defined as
one or more TRBs. The Chain bit is used to identify the TRBs that
comprise a TD. Refer to section 4.11.7 for more information on Link
TRB placement within a TD. On a Command Ring this bit is ignored by
the xHC.
I think that we should add XHCI_TRB_3_CHAIN_BIT to line 1895.
How do you think?
Hi Kohji,
The double word written at line 1895 does not set the "chain bit"
because this is the end of a transfer descriptor, TD. I'm unsure how
hardware interprets this bit, if setting the bit on the previous TRB
makes the next one connect to the previous one, or the other way around.
If setting this bit makes the TRB connect to the previous one, you are
correct. Else the current code is correct.
Thank you!
--HPS
src/sys/dev/usb/controller/xhci.c:
1879 /* fill out link TRB */
1880
1881 if (td_next != NULL) {
1882 /* link the current TD with the next one */
1883 td->td_trb[x].qwTrb0 =
htole64((uint64_t)td_next->td_self);
1884 DPRINTF("LINK=0x%08llx\n", (long
long)td_next->td_self);
1885 } else {
1886 /* this field will get updated later */
1887 DPRINTF("NOLINK\n");
1888 }
1889
1890 dword = XHCI_TRB_2_IRQ_SET(0);
1891
1892 td->td_trb[x].dwTrb2 = htole32(dword);
1893
1894 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1895 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT;
1896
1897 td->td_trb[x].dwTrb3 = htole32(dword);
1898
1899 td->alt_next = td_alt_next;
--
Best regards,
Kohji Okuno
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