--- John Hay <[EMAIL PROTECTED]> wrote:
> > 
> > | > There is a calibration step in the driver to
> determine the clock rate of th
> > | e 
> > | > AC97 link.  What you are seeing is the
> calibration step failing and setting
> > |  a 
> > | > bogus ac97 link rate.  I took a cursory look a
> couple of weeks back and it 
> > | > smelt like the timecounter initialization
> point changed, but haven't gotten
> > |  
> > | > around to looking closer and fixing the
> driver.
> > 
> > It's definitely nothing to do with the timecounter
> - quick test on other h/w 
> > along similar lines.  I don't access to an ich
> board to test on - it's 
> > probably obvious, but I'm not seeing it just now
> with visual inspection...
> 
> It doesn't look like it is the timecounters. I just
> added some printfs
> and it looks like this:
> 
> pcm0: measured ac97 link rate at 512000000 Hz
> t1 1.098359, t2 1.098363
> ociv 0, nciv 1, bytes 8192
> tsc1 445813142, tsc2 445821922, diff 8780
> 
> The tsc values are just from rdtsc(), I added tsc1 =
> rdtsc() just above
> the first microtime() and tsc2 just after the last.
> My machine is a 1.8G
> P4 (ICH2), so the timecounter values seem correct.
> 
> I have kernel around the middle of Feb that gets the
> value right and one
> from March 4 that gets it all wrong.
> 
> John
> -- 
> John Hay -- [EMAIL PROTECTED] /
> [EMAIL PROTECTED]
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I also see this problem.  On my machine, I dumped the
t1 and t2 variables - there's only about 3 microsecond
difference!.

It seems the calibration loop is entered, but that CIV
is immediately updated to the next index, thus getting
out of the loop after about 3-4 microseconds.

I thought something with the setup of the registers or
maybe a blocksize issue, but I'm getting out of my
element here.

I can try various testing and debug code if needed.

Chuck McCrobie
[EMAIL PROTECTED]

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