* Ruslan Ermilov <[EMAIL PROTECTED]> [ Date: 2003-07-30 ]
[ w.r.t. Re: make -U ]
> On Wed, Jul 30, 2003 at 04:23:20PM -0500, Juli Mallett wrote:
> > * Ruslan Ermilov <[EMAIL PROTECTED]> [ Date: 2003-07-30 ]
> > [ w.r.t. make -U ]
> > > Sorry, I've accidentally dropped an email about `make -U'.
> > >
> > > I think that it's not needed, since the functionality can
> > > easily be achieved by running "make FOO=", i.e., assigning
> > > an empty value. Remember that command line variables take
> > > precedence over globals, so the following makefile,
> > >
> > > FOO+= bar
> > >
> > > all:
> > > @echo ${FOO}
> > >
> > > when run as ``make FOO=foo'', will print just ``foo''.
> >
> > Does that work for the .if defined() case, too? Makefiles can grow
> > to be more complex than just that sort of stuff, after all :)
> >
> Not sure what do you mean. The "make -U FOO" was support to
> undefine the FOO variable, as it the ``.undef FOO'' was called
> at the end of makefile. Of course, setting FOO= on a command
> line still gets you a "defined" variable, but
>
> .if defined(FOO) && !empty(FOO)
>
> should do the trick. Try this out with "make FOO=":
>
> FOO= bar
>
> all:
> .if defined(FOO) && !empty(FOO)
> @echo FOO is set
> .endif
Why go thru those contortions? I sometimes use "make FOO=" to define
things. -U obviously has a place, if it not existing means I have to
have all these contortions to do a fairly obvious thing, yeah?
Thanx,
juli.
--
juli mallett. email: [EMAIL PROTECTED]; efnet: juli; aim: bsdflata;
i have lost my way home early - i don't care cause i won't stay there.
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