Warner Losh <i...@harmony.village.org> writes: > In message <pine.bsf.4.05.9906191302400.16699-100...@medulla.hippocampus.net> > Marc Nicholas writes: > : Hmmm...I always thought there was something "broke" inside Celerons to > : prevent SMP...maybe I'm wrong? Sure would be neat if you could run them > : SMP... > > What is "broke" about the Celerons is their cache. Without a good > cache sharing, you can't get good SMP performance. While you can run > a SMP Celeron machine, it won't scale as well as the PII version of > the chip. > > Warner
Do you mean the ones that don't have cache or the ones that have 128Kb cache on the chip? Is there that big of a hit of the cache is on the chip? I have seen some benchmarks and the system I have seemed to keep up well with a dual PII 400. I don't know how well it would scale though. -- Shaun Rowland rowl...@cis.ohio-state.edu http://www.cis.ohio-state.edu/~rowland/ To Unsubscribe: send mail to majord...@freebsd.org with "unsubscribe freebsd-hackers" in the body of the message
