on 03/06/2011 19:28 Jung-uk Kim said the following: > Unlike Intel, AMD did not guarantee "all TSCs reset to zero with RESET > IPI" before Bulldozer[1]. In fact, I tried to measure deltas between > cores when I started hacking on it using some crude heuristics, > somewhat like the OpenSolaris hack[2]. Basically, a dual-core AMD > Family 10h processor showed noticeably larger deltas than *two* > dual-core Intel Woodcrest Xeons'.
You are right. I haven't had any problems with my Athlon II system with forced smp_tsc, but testing shows that it has a measurable difference in TSC between cores. E.g. with the "tsc_check" code: cpus 0-1, min_write_time = 186, tdelta = 316 cpus 0-1, TSCs are considered to be OUT of sync > [1] I couldn't find any clues from their publicly available documents > whether they will implement (or need) additional mechanism for > multi-socket Bulldozer platforms. It only says something like "all > TSCs are synchronized with a clock source in north bridge". We will > see when AMD Valencia & Interlagos are available. :-) > [2] Unfortunately, there is no way to accurately measure it with > current generation hardware. Yeah, quite unfortunate. -- Andriy Gapon _______________________________________________ freebsd-hackers@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-hackers To unsubscribe, send any mail to "freebsd-hackers-unsubscr...@freebsd.org"
