> Date: Fri, 29 Jun 2001 13:14:58 -0700
> From: Matthew Rogers <[EMAIL PROTECTED]>
>
> Why not just use First in line, Next processor available ? Then you
> wouldn't care what processor did which task.
That was my question: Would the added complexity of "CPU affinity
hinting" be worth the reduction in cache misses and switching processes,
by preventing long-running processes from constantly switching CPUs?
FILNPA is fine for short-lived processes, but longer-running ones switch
CPUs, perhaps unnecessarily.
> Hmm, maybe even have each processor a dedicated memory space, and
> programmable functionality.
>
> Oops, that's a Field Programmable Gate Array, and there going to make
> Legacy computing look stupid.
FPGAs, mmmm. Transputers, mmmm. Neuromatrix, mmmm.
> In my mind, you have a need for multiprocessing Non-specific and
> Specific tasking.
>
> In some ways we are multiprocessing anyway on some level. Videocard 3d
> processing, sound card.
You mean that Winmodems and main memory-based video aren't the keys to
high performance? You mean that Intel is being silly when they justify
faster chips by saying "now you can eliminate three $20 DSPs by buying
our latest architecture"? :-)
> So why do we need a GOD chip, ie the "chipset" controlling access to
> processors and busses ?
>
> That's because that's the way it was done before the 286.
>
> Time to leave the bus. :)
Arguably so from a hardware standpoint. But, in the mean time, I was
trying to think of ways to help SMP performance. :-)
Eddy
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Date: Mon, 21 May 2001 11:23:58 +0000 (GMT)
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