Steven Smith <[EMAIL PROTECTED]> writes: > I don't know enough about Sparcs to even speculate how it's done > there.
The UltraSparc is a RISC processor, which amongst other things implies constant instruction size. Memory barriers take care of any cache coherence issues that may arise. DES -- Dag-Erling Smørgrav - [EMAIL PROTECTED] _______________________________________________ [EMAIL PROTECTED] mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-hackers To unsubscribe, send any mail to "[EMAIL PROTECTED]"
